![[Intel Navigation Header]](../../sites/develope/pix/header.gif){kind=small}
![[Intel Navigation Header]](mc51_map.gif)
|
|
| FEATURES | BENEFITS |
| 8-bit CPU optimized for event control | Efficient. Event control design |
| Boolean processing | Ease. Simple bit manipulation Flexibility. Enables single-chip designs |
| On-chip peripherals (timer/counters, serial ports, I/O ports, PCA, etc.) | Integration. High integration enables low-cost and low-chip count designs |
| Extensive software and hardware programming support | Easy to use. Simplifies your design cycle |
The Intel MCS 51 high speed microcontrollers are based on the MCS 51 microcontroller architecture. They are code and pin compatible with the existing MCS 51 microcontrollers and therefore are direct "drop-in" replacements to existing MCS 51 microcontroller applications.
| FEATURES | BENEFITS |
| Same instruction set as MCS® 51 controllers; software compatible with 80C51 | Synergy. Preserves design team knowledge and investment; no training required |
| Integration of 80C42-type host interface and keyboard scan | Single-chip solution. Saves board space and lowers system cost, especially in small notebook environment |
| Four channels, 8-bit A/D | Monitoring. Battery/CPU temperature and voltage monitoring |
| Interface for up to 32K of external memory | Flexibility. Accommodates larger code; flexibility in manufacturing flow |
| Five LED drivers | Reduces parts. Eliminates external discrete components |
| Two serial interfaces | Support. Provides external serial keyboard and mouse support |
| Additional power management register set, 3.3V operation | Efficiency. Enhanced power management function; provides greater power savings |
| 100LD PQFP and SQFP packages | Saves space. Small package size for board space savings |
| FEATURES | BENEFITS |
|---|---|
| Same instruction set as MCS 51 controllers | Synergy. Preserves code and knowledge investment |
| Direct drive LED outputs (13mA current sink capability) | Reduces parts. Reduce components cost and board space |
| 20pF on-chip cap for RC resonator (4-6 MHz selectable frequency) |
Cost effective. External crystal not required |
| Integrated power-on-reset circuitry | Integration. Cost and space savings |
| 8 dedicated Key Scan Input pins | Efficiency. With external interrupts for power management |
| 16 dedicated Key Scan Output pins with Quasi-bidirectional port drivers | Flexibility. No external resistors required and flexible board design |
| Clock/Data drivers to host |
Enhancement. Reduce component costs and provide efficient power management and compatibility |
| 128B RAM with 128 bits that are bit-addressable | Control. Code flexibility and easier control |
Keyboard Hardware Using 83C51KB
| FEATURES | BENEFITS |
| Same instruction set as MCS® 51 microcontrollers and is software compatible with 80C51 | Synergy. Preserves design team knowledge and investment; no training required |
| Enhanced interrupt structure with:
|
Flexibility. Flexible and comprehensive interrupt handling capacity for interrupt-intensive applications; reduces CPU overhead to define proper interrupt routing for heavy interrupt-driven applications. |
| 8-channel, 8-bit A/D converter:
|
A/D conversions. Intelligent, accurate A/D conversions allow:
|
| Two programmable counter arrays | Precision. Precise event timing measurement and control capabilities |
| Half-duplex synchronous serial port | Peripherals. More I/O peripherals expansion, such as off-chip (EEPROM) |
| FEATURES | BENEFITS |
| Same instruction set as MCS 51 microcontrollers; software compatible with 80C51 | Synergy. Preserves design team knowledge/investment; no training required |
| Fast data transfer with global serial channel | Effective. High effective data-rate throughput |
| Serial protocol | Cost effective. Cheaper and can be more reliable than parallel communications; easy to add and subtract nodes |
| Dual DMA channels | Efficient. Frees CPU for other tasks; on-chip DMA controller simplifies system design and reduces board space |
| SDLC and other HDLC subsets | Compatible. Supports proprietary and emerging ISDN applications such as PABX linecards and terminal adapters, and other proprietary networks as in programmable logic controllers |
| Carrier sense multiple-access/collision detect | Compatible. Supports IEEE 8023 defined access and other proprietary access methods |
| Deterministic collision resolution scheme | Unique. Determines worst-case access time; allows CSMA/CD to be used in real-time control environments; combines some of the best features of traditional methods-deterministic protocol with no polling overhead |
Project Builder Kits are low-cost (below US $200) development platforms that give design engineers all the hardware and software tools needed to fully evaluate device features and performance. These turn-key kits provide tools for every stage of the project design cycle.
Complete sets of development utilities and C compilers are available through third-party vendors. Many third-party vendors also provide in-circuit emulator development tools. Select the Development Tools button at the top of the page to access our tools database.
| Register RAM (Bytes) | Timer/ Counters | Serial Port | Analog Input Channels | I/O Pins | Speed (MHz) | Process | Package | Security | Temp. | Key Features | ||
| Classic Family | ||||||||||||
| 80C31BH | ROMless | 128 | 2 | 1 | 0 | 32 | 12,16,20,24,33 | CHMOS | N, P, S | N/A | C, E, A, M | Power Save Modes |
| 80C51BH | 4K ROM | 128 | 2 | 1 | 0 | 32 | 12,16,20,24,33 | CHMOS | N, P, S | P | C, E, A, M | Power Save Modes |
| 87C51 | 4K EPROM | 128 | 2 | 1 | 0 | 32 | 12,16,20,24,33 | CHMOS | D, N, P, S | L3 | C, E, A, M | Three-Level Memory Lock |
| 80C32 | ROMless | 256 | 3 | 1 | 0 | 32 | 12,16,20,24,33 | CHMOS | N, P, S | N/A | C, E, A | Up-Down Timer/Cou |