MOTOROLA 68000 INSTRUCTION SET ============================== This file is Public Domain. It contains the Motorola 68000 instruction set, fully documented, in a manner conforming to the standards laid down in the official Motorola documentation. The information contained here should be sufficient not only to allow newcomers to 680x0 assembly language to famil- iarise themselves with the instruction set, but for more experienced 68000 programmers to devise the basis of their own assembler, containing as it does the actual machine words corresponding to each instruction in binary format. The file includes extra information: 1) Extra instructions found upon the 68010 processor, and where possible, some extra instructions found upon the 68020 processor. 2) Extra addressing modes found upon the 68020 processor. There are several conventions used here. The following convention is used to illustrate condition code status: X N Z V C - 0 1 * U - Flag unchanged by operation 0 Flag set to 0 by operation 1 Flag set to 1 by operation * Flag changed functionally according to operation U Flag undefined after operation Where instruction words are given, they are given in binary, with various bit fields picked out using various letter combinations. These bit fields in turn have their own explicit documentation within each instruction. The characters X, N, Z, V and C refer to those condition code bits throughout except where a different convention from below specifies otherwise. The following abbreviations are used in the documentation of the var- ious 68000 instructions: src Source Operand dst Destination Operand Dn Any Data Register An Any Address Register Rn Any 680x0 Register, be it Data or Address Register Xn Any 680x0 Register, be it Data or Address Register, in the context of an index register CCR Condition Code Register SR Status Register PC Program Counter Any Effective Address using a legal 680x0 addressing mode. #nnn Any Immediate Operand (10) Specifies BCD Operand op{N} Specifies bit N of Operand for 68000/68010. The main documentation will consist of two parts. The first part is the individual instructions and their descriptions, the second is a full list of possible addressing modes and condition code computations. Furthermore, some instructions are PRIVILEGED. This means that they can ONLY be executed when the 68000 is operating in SUPERVISOR mode (i.e., bit 13 of the status register is set). Attempting to execute these instruc- tions with the 68000 in USER mode will cause the 68000 to enter exception processing, and trap via the Privilege Violation exception vector. NOTES : Some warnings for programmers inclined to use various tricks: 1) All arithmetic performed upon address registers uses the ENTIRE 32 bits of the address register! WORD size operands are SIGN EXTENDED to 32 bits within the 68000 prior to the operation. Source operands are NOT affected, however. 2) MOVEM.W from memory to registers SIGN EXTENDS TO 32 BITS. THIS INCLUDES DATA REGISTERS! So, if using upper halves of data reg- isters to save important data, best to MOVEM.L to and from memory instead, otherwise the upper halves of the data registers will be corrupted! 3) To ensure correct testing for multiple-precision extended-bit arithmetic instructions (ADDX, SUBX), use something such as MOVEQ #0,D0 to set the Z flag prior to the ADDX/SUBX sequence. Then, testing for zero operands at the end of the operations will work correctly (unless other instructions in your arith- metic loop affect Z also!). 4) DIVS/DIVU take a 32-BIT SOURCE. The result is a 16-BIT DESTIN- ATION, and a 16-BIT REMAINDER. If an overflow occurs, then the destination is NOT AFFECTED. This holds for 68000/68010. For 68020 onwards, extended DIVS/DIVU instructions exist. 5) MULS/MULU take 16-BIT source and destination operands, but the result is a 32-BIT destination. So the upper half of Dn will be corrupted. If using upper halves of data registers to save important data, save the data somehow first. This holds for 68000/68010. For 68020 onwards, extended MULS/MULU instructions exist. 6) DBcc only affects low words of data registers. So two counters can be kept in one register and SWAPped as appropriate (see DBcc and SWAP below). 7) Since 68000 address pointers are 24-bit pointers, there are always 8 bits spare at the uppermost byte of an address reg- ister on the 68000. These can be used to mix flags data with address pointers. DO NOT USE THIS TRICK IF CODE IS INTENDED TO BE PORTABLE TO 68020/68030/68040 ENVIRONMENTS! These pro- cessors use the full 32 bits of an address register, and have a full 32-bit address space. Bus errors could result. See the Motorola documentation for more information. 8) Programmers extending the instruction set via LINEF instructions can do so with impunity on the 68000. On the 68020/68030/60840, this is NOT possible. LINEF instructions are used heavily by the 68881/68882 mathematics coprocessors for the 68020/68030, and the 68040 is effectively a 68030/68882 combination on one chip. So for higher 680x0 processors, treat LINEF with care. See Motorola docu- mentation for more information. 9) LINK/UNLK make recursive code simpler to write than on other pro- cessors. Exercise care with extraneous returns! If using so-called "married" recursive functions, ensure that there are no 'secret back-door exits' that bypass the stack cleaning routines! 68000 - The Instructions ======================== ABCD : Add Decimal With Extend. Operation : src(10) + dst(10) + X -> dst Assembler : ABCD Dy,Dx ABCD -(Ay),-(Ax) Attributes:size=Byte Description : Perform Binary Coded Decimal (BCD) addition of the source and destination operands, together with the Extend (X) bit of the CCR. The only legal addressing modes are those given above. This is a byte operation only. Condition Codes : X N Z V C * U * U * N Undefined V Undefined Z Cleared if nonzero result. UNCHANGED otherwise! C Set if DECIMAL carry generated. Cleared otherwise. X Set identically to C. Notes : Normally, the Z bit is set via programming (this is the PROGRAMMER'S responsibility) before the start of an ABCD operation. This allows successful tests upon completion of multiple-precision ABCD operations. Instruction Format: 1 1 0 0 X X X 1 0 0 0 0 M Y Y Y Instruction Fields: XXX : Register Rx field. Specifies which register is used for the destination operand, D0-D7 for ABCD Dy,Dx or A0-A7 for ABCD -(Ay),-(Ax) YYY : Register Ry field. Specifies which register is used for the source operand, D0-D7 for ABCD Dy,Dx or A0-A7 for ABCD -(Ay),-(Ax) M : R/M field. Specifies addressing mode. 0 : mode is ABCD Dy,Dx 1 : mode is ABCD -(Ay),-(Ax) ADD : Add Binary. Operation : src + dst -> dst Assembler : ADD ,Dn ADD Dn, Attributes:size=Byte,Word,Long Description : Add the source operand to the destination operand, and store the result in the dest- ination operand. The operation may be spec- ified to be byte, word or long in size. The mode of the instruction indicates which is the source and which is the destination operand. Condition Codes : X N Z V C * * * * * N Set if result negative when treated as 2's complement. Cleared otherwise. Z Set if result is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a binary carry is generated. Cleared otherwise. X Set identically to C. Instruction Format : 1 1 0 1 R R R M M M E E E A A A Instruction Fields : RRR : Register field. Specifies any data register D0-D7. MMM : Op-Mode field. Specifies operation type in accordance with the table: Byte Word Long Operation ---- ---- ---- --------- 000 001 010 ADD ,Dn 100 101 110 ADD Dn, EEE and AAA specify the effective address of the operand. The table of possible values of the EEE and AAA fields appears in the section describ- ing the addressing modes. The legal modes are: Source : All addressing modes. Destination : The following are ILLEGAL addressing modes: An offset(PC) offset(PC,Xn) #nnn All others are legal. Notes : 1) If the destination is a data register, then the ADD ,Dn form of the instruc- tion MUST be used. 2) ADDA is used for ADD ,An. ADDI is used for ADD #nnn, where is not a data register. ADDQ is also used for ADD #nnn, when possible. Most 68000 assemblers can automatically make this distinction. ADDA : Add Address Operation : src + dst -> dst Assembler : ADDA ,An Attributes:size=Word,Long Description : Add the source operand to the destination address register, and store the result in the destination address register. The size of the operation may be specified to be a word or long operation. NOTE:All address arithmetic on address registers is performed using the ENTIRE 32 bits of the address register. Word operands are sign-extended to 32 bits before adding. Condition Codes : NOT AFFECTED. Instruction Format : 1 1 0 1 R R R M M M E E E A A A Instruction Fields : RRR : Specifies one of the address registers A0-A7. This is ALWAYS the destination operand. MMM : Op-Mode field. Specifies the size of the operation. 011 : Word operation. See NOTE above. 111 : Long operation. EEE and AAA fields. Defined in addressing mode section below. All legal 68000 addressing modes are allowed for the source operand. ADDI : Add Immediate Operand Operation : immediate data + dst -> dst Assembler : ADDI #nnnn, Attributes:size=Byte,Word,Long Description : Add the immediate data contained in the instruction to the destination operand, and store the result in the destination location. NOTE:The contents of the immediate operand part of the instruction is as follows: Byte : 2nd word of operand, upper byte zero. Word : 2nd word of operand. Long : 2nd and 3rd word of operand. Extension words for complex addressing modes follows the immediate operand. Condition Codes : X N Z V C * * * * * N Set if result negative when treated as 2's complement. Cleared otherwise. Z Set if result is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a binary carry is generated. Cleared otherwise. X Set identically to C. Instruction Format : 0 0 0 0 0 1 1 0 S S E E E A A A W W W W W W W W B B B B B B B B L L L L L L L L L L L L L L L L Instruction Fields : SS : Size field. Specifies operation size. 00 = byte operation 01 = word operation 10 = long operation EEE : Destination Effective Address field. AAA : Destination (Address) Register field. EEE and AAA specify the effective address of the operand. The table of possible values of the EEE and AAA fields appears in the section describ- ing the addressing modes. The LEGAL modes are: Dn (An) (An)+ -(An) d(An) d(An,Xi) Abs.W Abs.L BBB... : Byte immediate data field. The immediate data is contained here. The WWW... field is set to zero (00000000 binary) and the LLL... field does not exist. WWW... : Word immediate data field. The immediate data occupies both WWW... and BBB... fields. The LLL... field does not exist. LLL... : Long immediate data field. The immediate data occupies all BBB, WWW and LLL fields, and the long word is divided as follows: WWW...BBB... HIGH word of data LLL... LOW word of data ADDQ : Add Immediate Quick Operand Operation : immediate data + dst -> dst Assembler : ADDQ #nnnn, Attributes:size=Byte,Word,Long Description : Add the immediate data contained in the instruction to the destination operand, and store the result in the destination location. The range of values for the immediate operand is 1 to 8, represented in the instruction by 0 to 7 (0 repre- senting a value of 8). The immediate data is automatically coerced to the operation size by the 68000. Condition Codes : X N Z V C * * * * * N Set if result negative when treated as 2's complement. Cleared otherwise. Z Set if result is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a binary carry is generated. Cleared otherwise. X Set identically to C. NOTE : Condition codes NOT AFFECTED if addition destination is an address register! Instruction Format : 0 1 0 1 D D D 0 S S E E E A A A Instruction Fields : DDD : Data field. 3 bits of immediate data, 0 representing a value of 8, 1-7 repre- senting those values repsectively. SS : Size field. Specifies operation size. 00 = byte operation 01 = word operation 10 = long operation EEE : Destination Effective Address field. AAA : Destination (Address) Register field. EEE and AAA specify the effective address of the operand. The table of possible values of the EEE and AAA fields appears in the section describ- ing the addressing modes. The LEGAL modes are: Dn An (Word and Long only) (An) (An)+ -(An) d(An) d(An,Xi) Abs.W Abs.L ADDX : Add With Extend Operation : src + dst + X -> dst Assembler : ADDX Dy,Dx ADDX -(Ay),-(Ax) Attributes:size=Byte,Word,Long Description : Add the source operand to the destination operand, along with the extend bit, and store the result in the destination loca- tion. Condition Codes : X N Z V C * * * * * N Set if result negative when treated as 2's complement. Cleared otherwise. Z Cleared if result is non-zero. Unchanged otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a binary carry is generated. Cleared otherwise. X Set identically to C. NOTE : Normally the Z bit is set via programming (e.g., using MOVEQ #0,D0) before the start of the operation. This allows successful tests for zero operands upon completion of multiple-precision operations. Instruction Format : 1 1 0 1 X X X 1 S S 0 0 R Y Y Y Instruction Fields : XXX : Register Rx field. Specifies the destination register, depending upon R field. SS : Size field. Specifies operation size. 00 = byte operation 01 = word operation 10 = long operation R : R/M field, specifies operation addressing mode. 0 : operation is ADDX Dy,Dx, and XXX,YYY fields specify data registers. 1 : Operation is ADDX -(Ay),-(Ax), and XXX,YYY fields specify address registers. YYY : Register Ry field. Specifies the source register, depending upon R field. AND : Logical AND operation Operation : src AND dst -> dst Assembler : AND ,Dn AND Dn, Attributes:size=Byte,Word,Long Description : Logically (bitwise) AND the source operand with the destination operand, and store the result in the destination location. Condition Codes : X N Z V C - * * 0 0 N Set if result negative when treated as 2's complement. Cleared otherwise. Z Set if result is zero. Cleared otherwise. V Always Cleared. C Always Cleared. X Not affected. Instruction Format : 1 1 0 0 R R R M M M E E E A A A Instruction Fields : RRR : Register field. Specifies any of the 8 data registers. MMM : Op-Mode field. Specifies operation according to: Byte Word Long Operation ---- ---- ---- --------- 000 001 010 AND ,Dn 100 101 110 AND Dn, EEE : Destination Effective Address field. AAA : Destination (Address) Register field. EEE and AAA specify the effective address of the operand. The table of possible values of the EEE and AAA fields appears in the section describ- ing the addressing modes. The LEGAL modes are: Source Operand: Dn (An) (An)+ -(An) d(An) d(An,Xi) Abs.W Abs.L d(PC) d(PC,Xi) #nnnn Destination Operand: (An) (An)+ -(An) d(An) d(An,Xi) Abs.W Abs.L NOTES : 1) If the destination is a data register, then it CANNOT be specified using destination addressing mode, but MUST use the destination Dn mode above instead. 2) ANDI is used when the source is immediate data. Most assemblers automatically make this distinc- tion. ANDI : Logical AND immediate Operation : immediate data AND dst -> dst Assembler : ANDI #nnnn, Attributes:size=Byte,Word,Long Description : Logically (Bitwise) AND the immediate data contained in the instruction to the destin- ation operand, and store the result in the destination location. NOTE:The contents of the immediate operand part of the instruction is as follows: Byte : 2nd word of operand, upper byte zero. Word : 2nd word of operand. Long : 2nd and 3rd word of operand. Extension words for complex addressing modes follows the immediate operand. Condition Codes : X N Z V C - * * 0 0 N Set if the most significant bit of the result is set. Cleared otherwise. Z Set if the result is zero. Cleared otherwise. V Always Cleared. C Always Cleared. X Not Affected. Instruction Format : 0 0 0 0 0 0 1 0 S S E E E A A A W W W W W W W W B B B B B B B B L L L L L L L L L L L L L L L L Instruction Fields : SS : Size field. Specifies the size of the operation. 00 = Byte operation. 01 = Word operation. 10 = Long operation. EEE : Destination Effective Address field. AAA : Destination (Address) Register field. EEE and AAA specify the effective address of the operand. The table of possible values of the EEE and AAA fields appears in the section describ- ing the addressing modes. The LEGAL modes are: Dn (An) (An)+ -(An) d(An) d(An,Xi) Abs.W Abs.L BBB... : Byte immediate data field. The immediate data is contained here. The WWW... field is set to zero (00000000 binary) and the LLL... field does not exist. WWW... : Word immediate data field. The immediate data occupies both WWW... and BBB... fields. The LLL... field does not exist. LLL... : Long immediate data field. The immediate data occupies all BBB, WWW and LLL fields, and the long word is divided as follows: WWW...BBB... HIGH word of data LLL... LOW word of data ANDI : Logical AND immediate to CCR Operation : immediate data AND CCR -> CCR Assembler : ANDI #nnnn,CCR Attributes:size=Byte Description : Logically (Bitwise) AND the immediate data contained in the instruction to the contents of the Condition Code Register, and store the result in the Condition Code Register (low 8 bits of Status Register). NOTE:The contents of the immediate operand part of the instruction is as follows: Byte : 2nd word of operand, upper byte zero. Extension words for complex addressing modes follows the immediate operand. Condition Codes : X N Z V C * * * * * N Cleared if Bit 3 of the operand is zero. Unchanged otherwise. Z Cleared if Bit 2 of the operand is zero. Unchanged otherwise. V Cleared if Bit 1 of the operand is zero. Unchanged otherwise. C Cleared if Bit 0 of the operand is zero. Unchanged otherwise. X Cleared if Bit 4 of the operand is zero. Unchanged otherwise. Instruction Format : 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 B B B B B B B B Instruction Fields: BBB... : Byte data instruction field. The immediate data is contained in this field. ANDI : Logical AND immediate to SR (PRIVILEGED INSTRUCTION) Operation : If 68000 in supervisor state THEN immediate data AND SR -> SR ELSE TRAP EXCEPTION (PRIVILEGE VIOLATION) Assembler : ANDI #nnnn,SR Attributes:size=Word Description : Logically (Bitwise) AND the immediate data contained in the instruction to the contents of the Status Register, and store the result in the Status Register. NOTE:The contents of the immediate operand part of the instruction is as follows: Word : 2nd word of operand. Extension words for complex addressing modes follows the immediate operand. Condition Codes : X N Z V C * * * * * N Cleared if Bit 3 of the operand is zero. Unchanged otherwise. Z Cleared if Bit 2 of the operand is zero. Unchanged otherwise. V Cleared if Bit 1 of the operand is zero. Unchanged otherwise. C Cleared if Bit 0 of the operand is zero. Unchanged otherwise. X Cleared if Bit 4 of the operand is zero. Unchanged otherwise. Instruction Format : 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 W W W W W W W W W W W W W W W W Instruction Fields: WWW... : Word data instruction field. The immediate data is contained in this field. ASL,ASR : Arithmetic Shift Operation : dst (shifted by count) -> dst Assembler : ASd Dx,Dy ASd #nnnn,Dy ASd Attributes:size=Byte,Word,Long Description : Arithmetically shift the bits of the destination operand in the direction specified. The carry bit receives the last bit shifted out of the operand. The shift count for the operation can be specified in two ways: 1) Immediate. The shift count value is 1-8. 2) Data Register. The value contained in the specified data register, modulo 64, is used. If the destination operand is a memory operand, then the shift count is ALWAYS 1, and the operand size is ALWAYS word sized. ASL : Operand is shifted left by the value of the shift count. Bits shifted out of the high order bit are copied to the C and X bits of the CCR. V bit indicates sign changes during the operation. ASR : Operand is shifted right by the value of the shift count. Bits shifted out of the low order bit are copied to the C and X bit of the CCR. The sign bit (high-order bit) is replicated into the now vacant high-order bits. Condition Codes : X N Z V C * * * * * N Set if result negative when treated as 2's complement. Cleared otherwise. Z Set if result is zero. Cleared otherwise. V Set if most significant bit is changed at any time during the operation. Cleared otherwise. C Set according to the last bit shifted out of the operation. Cleared for a shift count of zero. X Set according to the last bit shifted out of the operand. UNAFFECTED for a shift count of zero! Instruction Format (Register Shifts) : 1 1 1 0 C C C D S S L 0 0 R R R Instruction Fields : CCC : Count/Register field. If immediate count, CCC = 1-7 for a shift count of 7, 0 for a shift count of 8. If data register count, CCC = data register number for register Dx. The value contained in bits 0-5 of Dx is used as the shift count (i.e., Dx modulo 64). D : Direction field. Specifies shift direction. 0 = right shift 1 = left shift SS : Size field. Specifies the size of the operation. 00 = Byte operation. 01 = Word operation. 10 = Long operation. L : L/R field. Specifies shift count type. 0 = immediate shift count in CCC field. 1 = data register count, register in CCC field. RRR : Register field. Specifies any of the 8 data registers whose content is to be shifted. Instruction Format (Memory Shifts) : 1 1 1 0 0 0 0 D 1 1 E E E A A A Instruction Fields : D : Direction field. Specifies shift direction. 0 = right shift 1 = left shift EEE : Destination Effective Address field. AAA : Destination (Address) Register field. EEE and AAA specify the effective address of the operand. The table of possible values of the EEE and AAA fields appears in the section describ- ing the addressing modes. The LEGAL modes are: (An) (An)+ -(An) d(An) d(An,Xi) Abs.W Abs.L Bcc : Branch Conditionally (Also Including BRA) Operation : IF condition is TRUE THEN PC + d -> PC ELSE continue normal sequential operation Assembler : Bcc