Digital Signal Analyzer v1.00 08-Apr-98 Short decription ================ This program was made for following purposes: - working as 16-cnannel logic analyser - viewing #?.hst and #?.trf files from Altera's (IBM PeeCee) PLDSHELL software. Warning ======= This software works directly with IDE ATA interface. This fact may cause conflicts with IDE hard drives. Working with IDE hard drive (reads, writes to disk from another processes simultaneously) in parallel with this software isn't recommended. Author cannot be held responsible for any damage of hard drive information resulting from hard disk activity at the same time when DSA works. Files ===== dsa - DSA executable dsa_russian_doc - documentation in Russian lang. dsa_english_doc - this document Source/dsa.s - DSA source Source/dsa.inc - include for this source Scheme/dsa.sch - DSA scheme in PCAD 4.5 (IBM PeeCee) Scheme/dsa.png - DSA scheme in Portable Network Graphics format (use Visage, akPNG for viewing) DataFiles/osc16.dsa - test datagrams in DSA internal format DataFiles/xxx202.hst - test datagrams in PLDSHELL format DataFiles/28mhz_A1260_50_cas.dsa - /CAS datagram of SIMM installed in author's 68060 accelerator :) Requirements ============ - Hardware :) Not required for viewing existing datagrams. - Kickstart 2.0 or higher - Any CPU, but tested only on 68060. Starting ======== CLI only. Hardware ======== External Inputs --------------- strt_s1 start digitizer depending on level of strt_sw1 strt_s2 start digitizer depending on front of strt_sw2 There are two conditions for start digitizing: 1) when strt_s1 goes to definite level 2) when strt_s2 changes level to definitive front This allows to detect first addressing (front) after reset (level) stop_s1 stop digitizer depending on level of stop_sw1 stop_s2 stop digitizer depending on front of stop_sw2, if this level was not changed during 256 xclk clocks. Stop becomes if any of this conditions was true. xclk clock frequency, comes directly to static RAM addressing and synchronize all scheme. Max frequency is about 30-40MHz. xd15-xd0 16 digital inputs (channels). If you want, you can connect ADC to this inputs. This is an input signals and you can connect them in any combination. Internal Signals ---------------- There are two buttons in this scheme. but_strt - start digitizing but_stop - stop digitizing There are also six swithers in scheme. strt_sw1 - level for strt_s1 0 (on) - finds logical 0 on strt_s1 1 (off) - finds logical 1 on strt_s1 strt_sw2 - front for strt_s2 0 (on) - finds positive front (0->1) on strt_s2 1 (off) - finds negative front (1->0) on strt_s2 stop_sw1 - level for stop_s1 0 (on) - finds logical 0 on stop_s1 1 (off) - finds logical 1 on stop_s1 stop_sw2 - level holding for stop_s2 0 (on) - finds stop_s2 holding in logical 1 during 256 xclk's 1 (off) - finds stop_s2 holding in logical 0 during 256 xclk's stop_sw3 - 256 xclk's delay at any stopping 0 (on) - delay on 1 (off) - delay off stop_sw4 - stop at the end of RAM. If switch turned off, digitizing will be continued from RAM beginning. IDE interface signals /ide_ior, /ide_iow, /ide_cs0, /reset, ide_d15-ide_d0 Ports for reading $da2000 (IDE port 0) - next 16bit data and auto increment of address (similar to IDE data reading) $da2004 (IDE port 1) - init triggers and preparing for start (start and stop will not work without init) $da2008 (IDE port 2) - start $da200c (IDE port 3) - stop $da2010 (IDE port 4) - reset address counter to 0. Ports for writing $da2018 (IDE port 6) bit 4 (bit 12 for 16bit addressing) =0 master IDE HDD activate =1 DSA activate This is not full correct mechanism. HDD doesn't see DSA as slave and may not disable own ports. If you don't like this - write me and explain how to do scheme more correctly. But it works. ICs layout It is not ideal, but it is enough optimized. View from solder size: ----------------------------- | | | dd1 ide | dd2 dd3 dd4 sw-блок connector | dd5 dd6 dd7 dd8 | | dd9 dd10 dd11 dd12 ide | dd13 dd14 dd15 dd16 power | dd17 dd18 dd19 connector | dd20 dd21 dd22 dd23 | | dd24 dd25 dd26 dd27 | | dd28 dd29 dd30 dd31 dd32 | | | ---input signals------------- You must connect about 10 or more blocking capacitors with powering bus. Powering layout, view from solder size: ----------------------------- | | | | | | | |-ide | | | | | |-connector | ----------------------| | | | | | | |-ide | |-power | | | | | |-connector | ----------------------| | | | | | | | | | | | | | | | | | ---input signals------------- Components dd1 74ac175 dd2 74ac74 dd3 74ac138 dd4 74ac138 dd5 74ac74 dd6 74ac74 dd7 74ac74 dd8 74ac11 dd9 74ac00 dd10 74ac04 dd11 74ac08 dd12 74ac86 dd13 74ac74 dd14 74ac74 dd15 74ac74 dd16 74ac32 dd17 w24m512ak-15 or another static ram 64к x 8 dd18 w24m512ak-15 or another static ram 64к x 8 dd19 74ac244 dd20 74ac244 dd21 74ac21 dd22 74ac244 dd23 74ac244 dd24 74ac374 dd25 74ac21 dd26 74ac374 dd27 74ac21 dd28 74ac193 dd29 74ac193 dd30 74ac193 dd31 74ac193 dd32 74ac138 74AC series are recommended. You can use any series, but only 74AC give enough speed and performance. Scheme successfully works at 28MHz. Resistors are 2-5k Menu commands ============= File menu: Load DSA file loading (asl requester) Save DSA file writing Save as DSA file writing with specified name (asl requester) Import PLDSHELL file loading (asl requester) Export PLDSHELL file writing (asl requester) About about author Quit guess what :) Hardware menu: Get osc Start digitizing Refresh mode Start cycled digitizing, any key or menu item - quit Init osc Init digitizer Start osc Init digitizer and start Stop osc Stop Make osc Display datagrams from buffer Mouse click to datagram - move cursor. Button between two sliders on bottom border - field size adjust. Keyboard commands ================= "+", "-", "+" and "-" on keypad - scale (+shift - slower) arrows - move cursor on datagram "u" "d" - move datagram under cursor up and down Author ====== Author name: Sobolev Vladimir Olegovich Place: Russia, Ekaterinburg Phone: +7-3432-654708 FIDOnet: 2:5080/52.69 Amiganet: 39:245/200.3 E-mail: vsobolev@hotmail.com amiga_man@usa.net Config: A1260-50Mhz/32Mb Ram/3.5Gb Fujitsu HDD/15"CityStar/Acorp33600 This software and sources are FREEWARE. Comments ======== This software was developed as auxiliary tool for accelerators/scandoublers/etc development. Quality is not guaranteed. If you want to improve it, at the first try yourself, and then send me a result. I will be glad if you will not disturb me about every trifle. I am very busy, but I always be glad to hear your wishes. History ======= 1. 08-Apr-1998 v1.00 First public release. Many that I want doesn't done... Text translated to English by Russian Digital Computing http://rdc.cch.pmc.ru