The Log System

Schematic capture

Log supports schematic entry for documentation, simulation, and netlist creation. Schematic printouts can be previewed on-screen, and encapsulated Postscript and HPGL output file formats are supported. In addition, the input file format for the Chipmunk graphics editor Until is supported.

Netlist generation

Log can generate SPICE netlists for circuit schematics; Log can also generate NTK format netlists, also generated by the Chipmunk VLSI layout tool Wol . Log supports hierarchial netlist generation. Using Log, Wol, and Netcmp (a netlist comparison tool included in the Chipmunk supplementary toolkit), 50,000 transistor IC designs have been verified for layout-vs-schematic netlist equality. Alternatively, IC designers can use Log to generate SPICE schematics, to support netlist verification of layout generated with Magic; Gemini is often used as the netlist comparison tool in this situation.

Simulation data visualization

Log includes a simulator-independent service for graphically viewing and measuring simulation data, supporting an arbitrary number of traces. The service generates output data suitable for input to the commercial tool MATLAB, and to the Chipmunk data plotting tool View . In addition, a simple plotting tool is integrated into the data visualization system, supporting Postscript and HPGL formats, and the file format for the Chipmunk graphics editor Until .

Analog circuit simulation

Log includes a full-featured analog circuit simulation package, Analog, written by John Lazzaro. Circuit schematic editing and parameter adjustments can occur while the simulator is in operation, supporting the metaphor of a virtual lab workbench. Model components include MOS transistor models optimized for accurate simulation in the weak-inversion regime, and macromodels of several of the circuits featured in Carver Mead's book Analog VLSI and Neural Systems. Circuits of 64 nodes or less can be reasonably simulated in analog; hierarchial simulation is not presently supported.

Digital circuit simulation

Log includes a unit-time-delay digital circuit simulation package, Diglog, written by Dave Gillespie. Circuit schematic editing and parameter adjustments can occur while the simulator is in operation, supporting the metaphor of a virtual lab workbench. Circuit libraries include many 7400-series TTL parts, and hard macros for early Actel FPGAs. Hierarchial simulation is supported. Log is currently suggested for simulation of systems with a few hundred gates; an outstanding bug often results in corrupted schematics during digital simulation for designs significantly larger.

Custom gate creation

The log package includes a standalone gate editor, Loged, for creating custom gate icons. The simulation code for simple digital gates can be embedded during gate description using loged; complex digital gates and simulation code for analog circuits requires separate C code. Loged can also generate data-sheets showing gate symbols and attributed, the the Postscript format.

Log is the most popular Chipmunk tool, and has founded many uses in academia and industry. Log can serve as a cost-free alternative to commercial tools like ViewLogic, for users with simple needs. Integrated circuit designers use it as an inexpensive tools for netlist creation; educators use it for introductory digital logic courses; weak-inversion MOS circuit designs use it to simulate small circuits.

To learn more about Log, you can start exploring its detailed documentation .

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