The most concern was taken about the memory interface.
This speed below is derived from a bus clock of 66MHz. The actual
bandwidth may be higher or lower according to the actual board clock. The bus interface is designed to provide a bus bandwidth of 427 MB/s.
This can be achieved for cachable (memory) accesses. Non-cachable
accesses are performed as single accesses and reduce the bandwidth to
267 MB/s during transfer.
The memory bandwidth can decrease to 217 MB/s (88 MB/s non-cachable),
but this should only occur during blocking.
(However an PPC address arbitration has a minimum duration of 3 cycles.
Thus one-precessor-memory-only-single-accesses can deliver only a
maximum data rate of 178 MB/s. Remember that little difference between
bandwidth and data rate. This not relevant for bursts, since they have a
length of five cycles, transferring 32 Bytes
). Since the data rate requested by the PPC is normally lower than the
provided bandwidth, there is idle time left on the bus allowing to
intermix accesses of a second processor or the DMA-Controller. This
depends heavily upon the application. Tasks only moving data around
consume more bandwidth than for example ray tracers. This high bandwidth is achieved by implementing an extensively used
address-pipeline. The PPC supports a separate arbitration of the address
and data bus, so that (memory) cycles requiring latency don't occupy the
busses through waitstates. Transfer requests are stored in the address
pipeline and a command microcode is generated.
Only if the data bus was idle the address pipeline is bypassed and the
request forwarded directly to the following circuitry. SDRAMs can provide a maximum bandwidth of 533 MB/s, but since they are
DRAMS internally, they need some time to present/accept data. The cycles
needed for this is called l
atency. In order not to occupy the data bus
until a command completes, the data bus prediction unit precalculates
this latency with the information gathered from the microcode, thus
predicting, when the data bus will get idle. The (four) memory
controller schedule the memory commands according to this information.
This board provides four memory banks (two DIMM slots), so the blocking
should not appear too often. The PowerPC board directly resides on the Zorro bus. This grants a fast
connection to graphic cards and SCSI-controllers on this bus without
having to pass the (Fat/"Super"-) Buster bottleneck. So the bandwidth is
determined by the Zorro backplane and the participating devices only.
This board only supports Zorro-III protocol since only this provides an
accurate speed using DMA and burst mode. Zorro-II shows it's big
limitation especially when tranferring graphic data.
This is surely not the last word about Zorro-II, but there's nothi
ng
more to say for now. There is no way to support EDO or FPM DRAMs any more. At first it would
destroy all advantages of the pipelining concept, on the other hand the
DIMMs necessary for the SDRAM are not previously used by any amiga, so
that no large-capacity EDO-DIMM should be wasted. WarpOS will run on this board. Existing WarpUP Software should run, if
they don't make very special assumptions about hardware configuration
(e.g. MMU, memory _locations_, board speed). Safe harbour note:
This information reflects the current development status. Although
carefully 'collected', there is no guarantee that can be given for that.
Information contained herein may be subject to change without notice.
Yours,
Martin Schüler --------------------
Martin Schüler
m.schueler@escena.de
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