** ** file: distant.a ** ** Z80 instruction routines that are moved outside the 0-7FFF range of ** offsets from InstrBase. ** The labels are formed from prefixing the actual instruction label with a ** 'd_'. From the original label (within the 0-7FFF range) a direct jump ** (absolute addressing) is made to the d_ label. ** ========================================================================= ;First, standard instructions: ** Note that the SET and RES instructions are suitable choices, because ** (apart from taking a lot of space: each uses 10 modes * 8 bits * about ** 10-15 words, totalling almost 2 kb of code) their routines are very short ** in comparison with the opcode length and the time it takes for a real Z80 ** to perform them. ** RES b,m ** ** m[b] <- 0 ** ** m can be r, (HL) or (ii+d) ** ** Flags: not affected d_res_b_r MACRO d_Res_\1_\2 opcode_2_bytes bclr #\1,Z80_\2(TableB) skip 1 next ENDM d_res_b_H MACRO d_Res_\1_H opcode_2_bytes bclr #8+\1,HL ;H is in bits 8-15 of the register skip 1 next ENDM d_res_b_L MACRO d_Res_\1_L opcode_2_bytes bclr #\1,HL ;L is the low byte of the register skip 1 next ENDM d_res_b_A MACRO d_Res_\1_A opcode_2_bytes bclr #\1,A skip 1 next ENDM d_res_b_1HL1 MACRO d_Res_\1_1HL1 opcode_2_bytes getz HL,tmpD1 bclr #\1,tmpD1 putz tmpD1,HL ;(putz uses tmpD0) skip 1 next ENDM d_res_b_1ii1 MACRO d_Res_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bclr #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) skip 3 next ENDM d_res_b MACRO d_res_b_r \1,B d_res_b_r \1,C d_res_b_r \1,D d_res_b_r \1,E d_res_b_H \1 d_res_b_L \1 d_res_b_A \1 d_res_b_1HL1 \1 d_res_b_1ii1 \1,X d_res_b_1ii1 \1,Y ENDM d_res_b 0 d_res_b 1 d_res_b 2 d_res_b 3 d_res_b 4 d_res_b 5 d_res_b 6 d_res_b 7 ** ----- ** SET b,m ** ** m[b] <- 1 ** ** m can be r, (HL) or (ii+d) ** ** Flags: not affected d_set_b_r MACRO d_Set_\1_\2 opcode_2_bytes bset #\1,Z80_\2(TableB) skip 1 next ENDM d_set_b_H MACRO d_Set_\1_H opcode_2_bytes bset #8+\1,HL ;H is in bits 8-15 of the register skip 1 next ENDM d_set_b_L MACRO d_Set_\1_L opcode_2_bytes bset #\1,HL ;L is the low byte of the register skip 1 next ENDM d_set_b_A MACRO d_Set_\1_A opcode_2_bytes bset #\1,A skip 1 next ENDM d_set_b_1HL1 MACRO d_Set_\1_1HL1 opcode_2_bytes getz HL,tmpD1 bset #\1,tmpD1 putz tmpD1,HL ;(putz uses tmpD0) skip 1 next ENDM d_set_b_1ii1 MACRO d_Set_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bset #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) skip 3 next ENDM d_set_b MACRO d_set_b_r \1,B d_set_b_r \1,C d_set_b_r \1,D d_set_b_r \1,E d_set_b_H \1 d_set_b_L \1 d_set_b_A \1 d_set_b_1HL1 \1 d_set_b_1ii1 \1,X d_set_b_1ii1 \1,Y ENDM d_set_b 0 d_set_b 1 d_set_b 2 d_set_b 3 d_set_b 4 d_set_b 5 d_set_b 6 d_set_b 7 ** ------------------------------------------------------------------------- ;Then, undocumented instructions: ;More particularly, those that are relatively slow on a real Z80, ;and take up a lot of space. ; They should only be compiled if undocumented instructions ;actually are used, i.e. UNDOCINSTR_UNDEF is not set. IFND UNDOCINSTR_UNDEF ** RES r,b,(ii+d) ** ** (ii+d)[b] <- 0, r <- (ii+d) ** ** Resets bit b of (ii+d) and copies the result into register r. ** ** Flags: not affected d_res_r_b_1ii1 MACRO d_Res_\1_\2_1I\3_d1 opcode_3_bytes index I\3,tmpD1 getz tmpD1,tmpD2 bclr #\2,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) move.b tmpD2,Z80_\1(TableB) ;copy to register skip 3 next ENDM d_res_H_b_1ii1 MACRO d_Res_H_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bclr #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD2,(Work) move.w (Work),tmpD2 ELSE lsl.w #8,tmpD2 ENDC move.b HL,tmpD2 move.l tmpD2,HL ;copy to H skip 3 next ENDM d_res_L_b_1ii1 MACRO d_Res_L_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bclr #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) move.b tmpD2,HL ;copy to L skip 3 next ENDM d_res_A_b_1ii1 MACRO d_Res_A_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bclr #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) move.b tmpD2,A ;copy to A skip 3 next ENDM d_res_r_b MACRO d_res_r_b_1ii1 B,\1,\2 d_res_r_b_1ii1 C,\1,\2 d_res_r_b_1ii1 D,\1,\2 d_res_r_b_1ii1 E,\1,\2 d_res_H_b_1ii1 \1,\2 d_res_L_b_1ii1 \1,\2 d_res_A_b_1ii1 \1,\2 ENDM d_res_r MACRO d_res_r_b 0,\1 d_res_r_b 1,\1 d_res_r_b 2,\1 d_res_r_b 3,\1 d_res_r_b 4,\1 d_res_r_b 5,\1 d_res_r_b 6,\1 d_res_r_b 7,\1 ENDM do_ii d_res_r ** ----- ** RL r,(ii+d) ** ____________________________________ ** | | ** - C <- (ii+d)[7] <- ... (ii+d)[0] <- ** ** (ii+d) is rotated left one bit position, the previous value of ** Carry rotated into bit 0 and bit 7 rotated out to Carry. The ** result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * d_rl_r_1ii1 MACRO d_Rl_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rl_H_1ii1 MACRO d_Rl_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rl_L_1ii1 MACRO d_Rl_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rl_A_1ii1 MACRO d_Rl_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rl_to_r MACRO d_rl_r_1ii1 B,\1 d_rl_r_1ii1 C,\1 d_rl_r_1ii1 D,\1 d_rl_r_1ii1 E,\1 d_rl_H_1ii1 \1 d_rl_L_1ii1 \1 d_rl_A_1ii1 \1 ENDM do_ii d_rl_to_r ** ----- ** RLC r,(ii+d) ** _______________________________ ** | | ** C <--- (ii+d)[7] <- ... (ii+d)[0] <- ** ** (ii+d) is rotated left one bit position, bit 7 rotated into ** bit 0 and to Carry. The result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * d_rlc_r_1ii1 MACRO d_Rlc_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 rol.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rlc_H_1ii1 MACRO d_Rlc_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 rol.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rlc_L_1ii1 MACRO d_Rlc_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 rol.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rlc_A_1ii1 MACRO d_Rlc_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 rol.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rlc_to_r MACRO d_rlc_r_1ii1 B,\1 d_rlc_r_1ii1 C,\1 d_rlc_r_1ii1 D,\1 d_rlc_r_1ii1 E,\1 d_rlc_H_1ii1 \1 d_rlc_L_1ii1 \1 d_rlc_A_1ii1 \1 ENDM do_ii d_rlc_to_r ** ----- ** RR r,(ii+d) ** ____________________________________ ** | | ** -> (ii+d)[7] ... -> (ii+d)[0] -> C - ** ** (ii+d) is rotated right one bit position, the previous value of ** Carry rotated into bit 7 and bit 0 rotated out to Carry. The ** result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * d_rr_r_1ii1 MACRO d_Rr_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rr_H_1ii1 MACRO d_Rr_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rr_L_1ii1 MACRO d_Rr_L_1I\1_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rr_A_1ii1 MACRO d_Rr_A_1I\1_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.w #1,stCCR roxr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rr_to_r MACRO d_rr_r_1ii1 B,\1 d_rr_r_1ii1 C,\1 d_rr_r_1ii1 D,\1 d_rr_r_1ii1 E,\1 d_rr_H_1ii1 \1 d_rr_L_1ii1 \1 d_rr_A_1ii1 \1 ENDM do_ii d_rr_to_r ** ----- ** RRC r,(ii+d) ** _______________________________ ** | | ** -> (ii+d)[7] <- ... (ii+d)[0] ---> C ** ** (ii+d) is rotated right one bit position, bit 0 rotated into ** bit 7 and to Carry. The result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * d_rrc_r_1ii1 MACRO d_Rrc_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ror.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rrc_H_1ii1 MACRO d_Rrc_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ror.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rrc_L_1ii1 MACRO d_Rrc_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ror.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rrc_A_1ii1 MACRO d_Rrc_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ror.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_rrc_to_r MACRO d_rrc_r_1ii1 B,\1 d_rrc_r_1ii1 C,\1 d_rrc_r_1ii1 D,\1 d_rrc_r_1ii1 E,\1 d_rrc_H_1ii1 \1 d_rrc_L_1ii1 \1 d_rrc_A_1ii1 \1 ENDM do_ii d_rrc_to_r ** ----- ** SET r,b,(ii+d) ** ** (ii+d)[b] <- 1, r <- (ii+d) ** ** Sets bit b of (ii+d) and copies the result into register r. ** ** Flags: not affected d_set_r_b_1ii1 MACRO d_Set_\1_\2_1I\3_d1 opcode_3_bytes index I\3,tmpD1 getz tmpD1,tmpD2 bset #\2,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) move.b tmpD2,Z80_\1(TableB) ;copy to register skip 3 next ENDM d_set_H_b_1ii1 MACRO d_Set_H_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bset #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD2,(Work) move.w (Work),tmpD2 ELSE lsl.w #8,tmpD2 ENDC move.b HL,tmpD2 move.l tmpD2,HL ;copy to H skip 3 next ENDM d_set_L_b_1ii1 MACRO d_Set_L_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bset #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) move.b tmpD2,HL ;copy to L skip 3 next ENDM d_set_A_b_1ii1 MACRO d_Set_A_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD1 getz tmpD1,tmpD2 bset #\1,tmpD2 putz tmpD2,tmpD1 ;(putz uses tmpD0) move.b tmpD2,A ;copy to A skip 3 next ENDM d_set_r_b MACRO d_set_r_b_1ii1 B,\1,\2 d_set_r_b_1ii1 C,\1,\2 d_set_r_b_1ii1 D,\1,\2 d_set_r_b_1ii1 E,\1,\2 d_set_H_b_1ii1 \1,\2 d_set_L_b_1ii1 \1,\2 d_set_A_b_1ii1 \1,\2 ENDM d_set_r MACRO d_set_r_b 0,\1 d_set_r_b 1,\1 d_set_r_b 2,\1 d_set_r_b 3,\1 d_set_r_b 4,\1 d_set_r_b 5,\1 d_set_r_b 6,\1 d_set_r_b 7,\1 ENDM do_ii d_set_r ** ----- ** SLA r,(ii+d) ** ** C <- (ii+d)[7] <- ... (ii+d)[0] <- 0 ** ** (ii+d) is shifted left one bit position, a zero shifted into ** bit 0 and bit 7 shifted out to Carry. (Arithmetic/logical ** shift.) The result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * ** Note: for the 680x0 arithmetic shift instructions, the V flag is ** set if the sign bit of the operand changes at any time during the ** operation, and cleared otherwise. For the logical shifts, V is always ** cleared. For this reason, Z80 'Sla' uses 680x0 'LSL'. d_sla_r_1ii1 MACRO d_Sla_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sla_H_1ii1 MACRO d_Sla_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sla_L_1ii1 MACRO d_Sla_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sla_A_1ii1 MACRO d_Sla_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sla_to_r MACRO d_sla_r_1ii1 B,\1 d_sla_r_1ii1 C,\1 d_sla_r_1ii1 D,\1 d_sla_r_1ii1 E,\1 d_sla_H_1ii1 \1 d_sla_L_1ii1 \1 d_sla_A_1ii1 \1 ENDM do_ii d_sla_to_r ** ----- ** SLL r,(ii+d) ** ** C <- (ii+d)[7] <- ... (ii+d)[0] <- 1 ** ** 'Shift Left Logically' with autocopy to register. (ii+d) is ** shifted left one bit position, bit 7 shifted out to Carry and a ** one (1) shifted into bit 0. The result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * ** Note: to get the flags set properly after the shift (in particular, Z ** should not be set because of the one shifted into bit 0, and we want to ** clear V for the parity test), we use the 680x0 ROXL instruction after ** explicitly setting the extend bit. d_sll_r_1ii1 MACRO d_Sll_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ori #$10,CCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sll_H_1ii1 MACRO d_Sll_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ori #$10,CCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sll_L_1ii1 MACRO d_Sll_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ori #$10,CCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sll_A_1ii1 MACRO d_Sll_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 ori #$10,CCR roxl.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sll_to_r MACRO d_sll_r_1ii1 B,\1 d_sll_r_1ii1 C,\1 d_sll_r_1ii1 D,\1 d_sll_r_1ii1 E,\1 d_sll_H_1ii1 \1 d_sll_L_1ii1 \1 d_sll_A_1ii1 \1 ENDM do_ii d_sll_to_r ** ----- ** SRA r,(ii+d) ** ** (ii+d)[7] ... -> (ii+d)[0] -> C ** ** (ii+d) is shifted right one bit position, bit 0 shifted out to ** Carry while bit 7 remains unchanged. (Arithmetic shift.) The ** result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * ** Note: for the 680x0 arithmetic shift instructions, the V flag is ** set if the sign bit of the operand changes at any time during the ** operation, and cleared otherwise. Since ASR preserves the sign bit, ** it always clears V. d_sra_r_1ii1 MACRO d_Sra_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 asr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sra_H_1ii1 MACRO d_Sra_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 asr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sra_L_1ii1 MACRO d_Sra_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 asr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sra_A_1ii1 MACRO d_Sra_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 asr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_sra_to_r MACRO d_sra_r_1ii1 B,\1 d_sra_r_1ii1 C,\1 d_sra_r_1ii1 D,\1 d_sra_r_1ii1 E,\1 d_sra_H_1ii1 \1 d_sra_L_1ii1 \1 d_sra_A_1ii1 \1 ENDM do_ii d_sra_to_r ** ----- ** SRL r,(ii+d) ** ** 0 -> (ii+d)[7] ... -> (ii+d)[0] -> C ** ** (ii+d) is shifted right one bit position, bit 0 shifted out ** to Carry and a zero shifted into bit 7. (Logical shift.) The ** result is copied into register r. ** ** Flags: S Z H P N C ** * * 0 * 0 * d_srl_r_1ii1 MACRO d_Srl_\1_1I\2_d1 opcode_3_bytes index I\2,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,Z80_\1(TableB) ;copy to register IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_srl_H_1ii1 MACRO d_Srl_H_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) IFNE PROCESSOR<68030 move.b tmpD1,(Work) move.w (Work),tmpD1 ELSE lsl.w #8,tmpD1 ENDC move.b HL,tmpD1 move.l tmpD1,HL ;copy to H IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_srl_L_1ii1 MACRO d_Srl_L_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,HL ;copy to L IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_srl_A_1ii1 MACRO d_Srl_A_1I\1_d1 opcode_3_bytes index I\1,tmpD2 clr.w tmpD1 getz tmpD2,tmpD1 lsr.b #1,tmpD1 putccr stCCR parity tmpD1 putz tmpD1,tmpD2 ;(putz uses tmpD0) move.b tmpD1,A ;copy to A IFD BCDFLAGS clr.b Z80_BCDF(TableB) ;clear H and N ENDC skip 3 next ENDM d_srl_to_r MACRO d_srl_r_1ii1 B,\1 d_srl_r_1ii1 C,\1 d_srl_r_1ii1 D,\1 d_srl_r_1ii1 E,\1 d_srl_H_1ii1 \1 d_srl_L_1ii1 \1 d_srl_A_1ii1 \1 ENDM do_ii d_srl_to_r ENDC ;IFND UNDOCINSTR_UNDEF ** =========================================================================