;************************** ADB.EQU Header - Sets up EQUates *************

;*** TESTING *** BITS USED IN TESTING FOR I/O

; *** BOOLEANS USED TO SELECT PART BEING USED
                        ; Only One Part May Be selected at a time
C54     equ     FALSE   ;TRUE    
C55     equ     FALSE         
C56     equ     TRUE    ;FALSE   
C57     equ     FALSE

LED     equ     00h     ; *** AN LED ON LINE RB0 INDICATES SWITCH PRESSED
Switch  equ     01h     ; *** 'Switch' USED FOR A SWITCH ON LINE RB1 AND
                        ; ***    AS A FLAG IN FLAGS2 FOR DEBOUNCING

SHIFT   equ     38h     
BANG    equ     12h

DEBOUNC equ     08h     ; *** # OF TIMES TO LOOP TO ALLOW DEBOUNCE OF SWITCH




; *** BIT ASSIGNMENTS FOR I/O LINES & TRI-STATING

ADB     equ     00h     ; Line used for ADB - pin XX (16C54)
RA1     equ     01h     ; May be used as a Clock line TO another PIC
RA2     equ     02h     ; May be used as a Clock line FROM another PIC
RA3     equ     03h     ; May be used as a Data line between two PICs

TRI_IN  equ     01h     ; tri-state for ADB pin as input
TRI_OUT equ     00h     ; tri-state for ADB pin as output


;*** MISC. CONSTANTS

BYTE    equ     08h     ; Receive 8 bits in Command; count from 8 to 0
DEF_ADD equ     02h     ; default device address to start with (kybd)
DEF_HND equ     03h     ; default Handler Id. to start with (std. kybd)
OFFSET  equ     08h     ; offset to RAM address of the array of ADB 
                        ;   Data storage registers


;*** COMMAND MASKS:         MASK BITS FROM COMMAND REGISTER FOR: 

DEVMASK equ     0Fh     ; lower nibble holds Command (Talk, etc.) & Reg. #
ADDRMSK equ    0F0h     ; upper nibble holds the Device Address Number
CMDNIBL equ     0Fh     ; Command nibble from the address 
CMDTYPE equ     0Ch     ; Upper 2 Command bits indicate Talk, Listen, etc.
REGMASK equ     03h     ; Data Register Number bits from Command Nibble
FSRMASK equ     1Fh     ; FSR bits from the Command Nibble for RAM Address


;*** DATA COMMAND MASKS:    MASK DATA REGISTER 3a FOR: 

LOW_NBL equ     0Fh     ; Lower nibble from the 1st Data byte
HI_NIBL equ    0F0h     ; Upper nibble from the 1st Data byte


;*** CONSTANTS FOR MASKING OUT COMMAND NIBBLES (C_ indicates Command)

                        ; used to XOR if this is a:
C_TALK  equ     0Ch     ;   Talk Command
C_LISTN equ     08h     ;   Listen Command
C_RESET equ     00h     ;   Reset Command
C_FLUSH equ     01h     ;   Flush Command
C_RES_1 equ     04h     ;   Reserved Command 1
C_RES_2 equ     02h     ;   Reserved Command 2
C_RES_3 equ     03h     ;   Reserved Command 3


;*** DATA HANDLER ID MASKS: MASK DATA REGISTER 3b FOR:

SELFTST equ    0FFh     ; Self-Test mode
LISTEN1 equ      0h     ; unconditional address change
LISTEN2 equ    0FEh     ; address change if no collision detected
DEV_ACT equ    0FDh     ; address change if device activator is depressed


;*** BITS USED IN THE UPPER NIBBLE OF REGISTER 3a FOR SPECIAL ADB STATUS BITS

Resrvd3 equ     04h      ; reserved (Always 0)
Srq_Bit equ     05h      ; determines if Host will accept Service Requests
ExpEvnt equ     06h      ; indicates an Exceptional Event should take place
Always0 equ     07h      ; always set to 0


;*** ADB FLAG BITS IN THE "FLAGS1" REGISTER (F1 indicates 1st Flags register)

F1Attn  equ     00h     ; set to know if 2nd Task taking place during Attn
F1Reg3  equ     01h     ; Register 3 is being addressed
F1Talk  equ     02h     ; indicates to Tlt routine this is a Talk Command
F1Stop  equ     03h     ; set to indicate the Data Stop Bit is being sent
F1Lstn  equ     04h     ; indicates to Tlt routine this is a Listen Command
F1Sent1 equ     05h     ; 1st byte of Data Register has been sent
F1Rcvd1 equ     06h     ; 1st byte of Data Register has been received
F1Cllsn equ     07h     ; set to indicate that a collision occurred


;*** FLAG BITS IN THE "FLAGS2" REGISTER (F2 indicates 2nd Flags register)

F2Srq   equ     00h     ; indicate that Srq should be issued
;               01h       Switch, defined above for PORT_B, also used as a Flag
F2DActv equ     02h     ; change address if Device Activator is Depressed
F2STest equ     03h     ; set to indicate a device Self Test is to be performed
F2SFail equ     04h     ; set to indicate that the Device Self-Test Failed
F2DRcvd equ     05h     ; set when data is received for 2nd Application Task
F2DSend equ     06h     ; set to indicate to Talk that Data needs to be sent
F2DMore equ     07h     ; set in 2nd Task to indicate Data remains to be sent


;*** TIMING DEFINITIONS
                             ; These values currently used for clock at 4Mhz:
PrSclr1 equ     .4           ;   this is used when the RTCC is being prescaled
PrSclr2 equ     .1           ;   this is used when the RTCC is not prescaled

ATT_MIN equ     .776/PrSclr1 ; Attn lower limit: 800 - 3% tolerance = 776 usecs
ATT_MAX equ     .824/PrSclr1 ; Attn upper limit: 800 + 3% tolerance = 824 usecs
TSK2MIN equ     .500/PrSclr1 ; time given to 2nd Task during Attn Signal
TSK2MAX equ     .900/PrSclr1 ; time given to 2nd Task after Data Sent/Received
SYNC    equ     .72/PrSclr2  ; Sync with extra tolerance after Attn is detected
BIT_TST equ     .50/PrSclr2  ; if time is < 50 = 1 bit, & > 50 = 0 bit
MAX_BIT equ     .72/PrSclr2  ; Maximum time line can be low for a bit   
BITCELL equ     .104/PrSclr2 ; Maximum time for a bit cell = 104 usecs
TLT_MIN equ     .140/PrSclr2 ; Stop to Start minimum time = 140 usecs
TLT_MAX equ     .250/PrSclr2 ; Stop to Start maximum time = 260 usecs
TLT_MID equ     .180/PrSclr2 ; Stop to Start median time  = 208 usecs
SRQ_MAX equ     .296/PrSclr1 ; amount of time to hold for a Service ReQuest 

 ; NOTE: for RTCC timing of sending bits, some extra time is allowed for 
 ; instruction cycles between the end of the bit and the start of the next bit

LOW1BIT equ     .22/PrSclr2  ; low time for a 1 bit
HI_1BIT equ     .50/PrSclr2  ; hi time  for a 1 bit
LOW0BIT equ     .56/PrSclr2  ; low time for a 0 bit
HI_0BIT equ     .20/PrSclr2  ; hi time  for a 0 bit


;*** ADB DATA REGISTERS - 2 BYES FOR EACH OF REGISTERS 0, 1, 2, and 3

ADB_REG ORG     08h     ; ORIGIN FOR ADB DATA REGISTERS
Reg0a   RES     01h     ; 8
Reg0b   RES     01h     ; 9
Reg1a   RES     01h     ; A
Reg1b   RES     01h     ; B
Reg2a   RES     01h     ; C
Reg2b   RES     01h     ; D
Reg3a   RES     01h     ; E
Reg3b   RES     01h     ; F


;*** VARIABLE REGISTERS FOR STORAGE, FLAGS, THE TIME VARIABLE, THE COUNTER, 
;                       & RANDOM VALUES

STORAGE ORG     10h     ; ORIGIN FOR MISC. DATA VARIABLES
TmpReg1 RES     01h     ; 10 - temporary registers where Data is sent from & 
TmpReg2 RES     01h     ; 11 -  received; NOTE: THESE 2 MUST BE IN THIS ORDER
RegNum  RES     01h     ; 12 - holds current ADB Data Reg.# - NOT a RAM address
RAMaddr RES     01h     ; 13 - holds RAM address of ADB Data Reg.#
Flags1  RES     01h     ; 14 - two Flags registers used by ADB & 2nd
Flags2  RES     01h     ; 15 -   Application Task
CmdByte RES     01h     ; 16 - holds the Command Byte
BitCntr RES     01h     ; 17 - counts down when sending or receiving bits
Random  RES     01h     ; 18 - stores Random Address sent in Talk routine
TimeVar RES     01h     ; 19 - used with RTCC for all ADB timing
Tsk2Var RES     01h     ; 1A - used with RTCC for timing during 2nd Task


;*** REGISTERS STILL AVAILABLE

TmpCtr1 RES     01h     ; 1B
TmpFlg1 RES     01h     ; 1C
TmpFlg2 RES     01h     ; 1C
TmpFlg3 RES     01h     ; 1D
TmpFlg4 RES     01h     ; 1E


PROGRAM ORG     00h     ; origin for program
