;EXCEPT.68K	APR-09-89
;Error handler for unassigned exception vectors.

;WARNINGS:
;This assumes that there are no user vectors (locs $100 thru $3FF), thus
; this will not work on the Stride.
; This is set up to restart Apex when the Mac's interrupt button is
; pressed.

	NOLIST
	INCLUDE	SYSPAG		;get Apex system parameters
	LIST

	ORG	0

;EXCEPTION VECTORS:
	DC.L	TABLE+0		;0 Reset: Initial Interrupt Stack Ptr
	DC.L	TABLE+2		;1 Reset: Initial Program Counter
	DC.L	TABLE+4		;2 Bus Error
	DC.L	TABLE+6		;3 Address Error
	DC.L	TABLE+8		;4 Illegal Instruction
	DC.L	TABLE+10	;5 Divide by Zero
	DC.L	TABLE+12	;6 CHK, CHK2 Instruction
	DC.L	TABLE+14	;7 cpTRAPcc, TRAPcc, TRAPV Instructions
	DC.L	TABLE+16	;8 Privilege Violation
	DC.L	TABLE+18	;9 Trace
	DC.L	TABLE+20	;10 Line 1010 Emulator
	DC.L	TABLE+22	;11 Line 1111 Emulator
	DC.L	TABLE+24	;12 (Unassigned Reserved)
	DC.L	TABLE+26	;13 Coprocessor Protocol Violation
	DC.L	TABLE+28	;14 Format error
	DC.L	TABLE+30	;15 Uninitialized Interrupt
	DC.L	TABLE+32	;16 (Unassigned Reserved)
	DC.L	TABLE+34	;17 (Unassigned Reserved)
	DC.L	TABLE+36	;18 (Unassigned Reserved)
	DC.L	TABLE+38	;19 (Unassigned Reserved)
	DC.L	TABLE+40	;20 (Unassigned Reserved)
	DC.L	TABLE+42	;21 (Unassigned Reserved)
	DC.L	TABLE+44	;22 (Unassigned Reserved)
	DC.L	TABLE+46	;23 (Unassigned Reserved)
	DC.L	TABLE+48	;24 Spurious Interrupt
	DC.L	TABLE+50	;25 Level 1 Interrupt Auto Vector
	DC.L	TABLE+52	;26 Level 2 Interrupt Auto Vector
	DC.L	TABLE+54	;27 Level 3 Interrupt Auto Vector
	DC.L	TABLE+56	;28 Level 4 Interrupt Auto Vector
	DC.L	TABLE+58	;29 Level 5 Interrupt Auto Vector
	DC.L	TABLE+60	;30 Level 6 Interrupt Auto Vector
	DC.L	TABLE+62	;31 Level 7 Interrupt Auto Vector
	DC.L	TABLE+64	;32 Trap #0 Instruction Vector
	DC.L	TABLE+66	;33 Trap #1 Instruction Vector
	DC.L	TABLE+68	;34 Trap #2 Instruction Vector
	DC.L	TABLE+70	;35 Trap #3 Instruction Vector
	DC.L	TABLE+72	;36 Trap #4 Instruction Vector
	DC.L	TABLE+74	;37 Trap #5 Instruction Vector
	DC.L	TABLE+76	;38 Trap #6 Instruction Vector
	DC.L	TABLE+78	;39 Trap #7 Instruction Vector
	DC.L	TABLE+80	;40 Trap #8 Instruction Vector
	DC.L	TABLE+82	;41 Trap #9 Instruction Vector
	DC.L	TABLE+84	;42 Trap #A Instruction Vector
	DC.L	TABLE+86	;43 Trap #B Instruction Vector
	DC.L	TABLE+88	;44 Trap #C Instruction Vector
	DC.L	TABLE+90	;45 Trap #D Instruction Vector
	DC.L	TABLE+92	;46 Trap #E Instruction Vector
	DC.L	TABLE+94	;47 Trap #F Instruction Vector
	DC.L	TABLE+96	;48 FPCP BRA or SET on Unordered Cond
	DC.L	TABLE+98	;49 FPCP Inexact Result
	DC.L	TABLE+100	;50 FPCP Divide by Zero
	DC.L	TABLE+102	;51 FPCP Underflow
	DC.L	TABLE+104	;52 FPCP Operand Error
	DC.L	TABLE+106	;53 FPCP Overflow
	DC.L	TABLE+108	;54 FPCP Signaling NAN
	DC.L	TABLE+110	;55 (Unassigned Reserved)
	DC.L	TABLE+112	;56 PMMU Configuration
	DC.L	TABLE+114	;57 PMMU Illegal Operation
	DC.L	TABLE+116	;58 PMMU Access Level Violation
	DC.L	TABLE+118	;59 (Unassigned Reserved)
	DC.L	TABLE+120	;60 (Unassigned Reserved)
	DC.L	TABLE+122	;61 (Unassigned Reserved)
	DC.L	TABLE+124	;62 (Unassigned Reserved)
	DC.L	TABLE+126	;63 (Unassigned Reserved)

;Long branches:
BUSERR	BRA	BUSER
ADDRERR	BRA	ADDRER
ILLERR	BRA	ILLER
DIVERR	BRA	DIVER
CHKERR	BRA	CHKER
TRPVERR	BRA	TRPVER
PRIVERR	BRA	PRIVER
TRACERR	BRA	TRACER
LINAERR	BRA	LINAER
LINFERR	BRA	LINFER
INTERR	BRA	INTER
INTBUTT	BRA	INTBUT
TRAPERR	BRA	TRAPER

;
;Jump table. The "return address" pushed on the stack by the BSR.S
; instruction is used to specify the entry.
;
TABLE	NOP			;0 Reset: Initial Interrupt Stack Ptr
	BSR.S	MISCERR		;1 Reset: Initial Program Counter
	BSR.S	BUSERR		;2 Bus Error
	BSR.S	ADDRERR		;3 Address Error
	BSR.S	ILLERR		;4 Illegal Instruction
	BSR.S	DIVERR		;5 Divide by Zero
	BSR.S	CHKERR		;6 CHK, CHK2 Instruction
	BSR.S	TRPVERR		;7 cpTRAPcc, TRAPcc, TRAPV Instructions
	BSR.S	PRIVERR		;8 Privilege Violation
	BSR.S	TRACERR		;9 Trace
	BSR.S	LINAERR		;10 Line 1010 Emulator
	BSR.S	LINFERR		;11 Line 1111 Emulator
	BSR.S	MISCERR		;12 (Unassigned Reserved)
	BSR.S	MISCERR		;13 Coprocessor Protocol Violation
	BSR.S	MISCERR		;14 Format error
	BSR.S	MISCERR		;15 Uninitialized Interrupt
	BSR.S	MISCERR		;16 (Unassigned Reserved)
	BSR.S	MISCERR		;17 (Unassigned Reserved)
	BSR.S	MISCERR		;18 (Unassigned Reserved)
	BSR.S	MISCERR		;19 (Unassigned Reserved)
	BSR.S	MISCERR		;20 (Unassigned Reserved)
	BSR.S	MISCERR		;21 (Unassigned Reserved)
	BSR.S	MISCERR		;22 (Unassigned Reserved)
	BSR.S	MISCERR		;23 (Unassigned Reserved)
	BSR.S	MISCERR		;24 Spurious Interrupt
	BSR.S	INTERR		;25 Level 1 Interrupt Auto Vector
	BSR.S	INTERR		;26 Level 2 Interrupt Auto Vector
	BSR.S	INTERR		;27 Level 3 Interrupt Auto Vector
	BSR.S	INTERR		;28 Level 4 Interrupt Auto Vector
	BSR.S	INTERR		;29 Level 5 Interrupt Auto Vector
	BSR.S	INTERR		;30 Level 6 Interrupt Auto Vector
	BSR.S	INTBUTT		;31 Level 7 Interrupt Auto Vector
	BSR.S	TRAPERR		;32 Trap #0 Instruction Vector
	BSR.S	TRAPERR		;33 Trap #1 Instruction Vector
	BSR.S	TRAPERR		;34 Trap #2 Instruction Vector
	BSR.S	TRAPERR		;35 Trap #3 Instruction Vector
	BSR.S	TRAPERR		;36 Trap #4 Instruction Vector
	BSR.S	TRAPERR		;37 Trap #5 Instruction Vector
	BSR.S	TRAPERR		;38 Trap #6 Instruction Vector
	BSR.S	TRAPERR		;39 Trap #7 Instruction Vector
	BSR.S	TRAPERR		;40 Trap #8 Instruction Vector
	BSR.S	TRAPERR		;41 Trap #9 Instruction Vector
	BSR.S	TRAPERR		;42 Trap #A Instruction Vector
	BSR.S	TRAPERR		;43 Trap #B Instruction Vector
	BSR.S	TRAPERR		;44 Trap #C Instruction Vector
	BSR.S	TRAPERR		;45 Trap #D Instruction Vector
	BSR.S	TRAPERR		;46 Trap #E Instruction Vector
	BSR.S	TRAPERR		;47 Trap #F Instruction Vector
	BSR.S	MISCERR		;48 FPCP BRA or SET on Unordered Cond
	BSR.S	MISCERR		;49 FPCP Inexact Result
	BSR.S	MISCERR		;50 FPCP Divide by Zero
	BSR.S	MISCERR		;51 FPCP Underflow
	BSR.S	MISCERR		;52 FPCP Operand Error
	BSR.S	MISCERR		;53 FPCP Overflow
	BSR.S	MISCERR		;54 FPCP Signaling NAN
	BSR.S	MISCERR		;55 PMMU Configuration
	BSR.S	MISCERR		;56 PMMU Illegal Operation
	BSR.S	MISCERR		;57 PMMU Access Level Violation
	BSR.S	MISCERR		;58 (Unassigned Reserved)
	BSR.S	MISCERR		;59 (Unassigned Reserved)
	BSR.S	MISCERR		;60 (Unassigned Reserved)
	BSR.S	MISCERR		;61 (Unassigned Reserved)
	BSR.S	MISCERR		;62 (Unassigned Reserved)
	BSR.S	MISCERR		;63 (Unassigned Reserved)
	NOP			;Required for short branch

;
;Miscellaneous exception error handler
;
MISCERR	MOVE.L	(SP)+,D0	;Pop PC (return address)
	SUBI.L	#TABLE,D0	;Vector number =
	ASR.L	#1,D0		; (PC - TABLE) >>1 -1
	SUBQ.L	#1,D0
	DIVU	#10,D0		;Store vector number into error
	ORI.W	#'0',D0		; message
	MOVE.B	D0,ERR20-2
	SWAP	D0
	ORI.W	#'0',D0
	MOVE.B	D0,ERR20-1

	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- EXCEPTION NO. __'
ERR20	DC.B	0
	JMP	VRELOD		;(For safety)

;
;Unassigned interrupt handler
;
INTER	MOVE.L	(SP)+,D0	;Pop PC (return address)
	SUBI.W	#TABLE,D0	;Interrupt auto vector number =
	ASR.W	#1,D0		; (PC - TABLE) >>1 -1 -25 +1
	SUBI.W	#25,D0

	ANDI.B	#$0F,D0		;Store interrupt auto vector number into
	ORI.B	#$30,D0		; error message
	MOVE.B	D0,INT20-1

;	ANDI	#$F8FF,SR	;Re-enable interrupts (to flash cursor)
	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- UNASSIGNED INTERRUPT AT LEVEL _'
INT20	DC.B	0
	JMP	VRELOD		;(For safety)

;
;Interrupt button handler (level 7)
;
INTBUT
;	ANDI	#$F8FF,SR	;Re-enable interrupts (to flash cursor)
	JMP	VRELOD		;Go to Apex

;
;Unassigned trap handler
;
TRAPER	MOVE.L	(SP)+,D0	;Pop PC (return address)
	SUBI.W	#TABLE,D0	;Trap number =
	ASR.W	#1,D0		; (PC - TABLE) >>1 -1 -32
	SUBI.W	#1+32,D0

	MOVE.B	HEXTBL-@-2(PC,D0.W),TRAP20-1
				;Store trap number into error message
	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- UNASSIGNED TRAP #$_'
TRAP20	DC.B	0
	JMP	VRELOD		;(For safety)

HEXTBL	ASCII	'0123456789ABCDEF'

;
;Other exception error handlers
;
BUSER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- BUS EXCEPTION'
	DC.B	0

ADDRER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- ADDRESS EXCEPTION'
	DC.B	0

ILLER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- ILLEGAL INSTRUCTION EXCEPTION'
	DC.B	0

DIVER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- DIVIDE BY ZERO EXCEPTION'
	DC.B	0

CHKER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- CHK INSTRUCTION EXCEPTION'
	DC.B	0

TRPVER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- TRAPV INSTRUCTION EXCEPTION'
	DC.B	0

PRIVER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- PRIVILEGE VIOLATION EXCEPTION'
	DC.B	0

TRACER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- TRACE EXCEPTION'
	DC.B	0

LINAER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- LINE 1010 EXCEPTION'
	DC.B	0

LINFER	ST	ERRTRAP		;Always trap
	JSR	VERROR
	ASCII	'- LINE 1111 EXCEPTION'
	DC.B	0
	JMP	VRELOD		;(For safety)


	IF @ > $400
	ERROR -- TOO BIG
	ENDIF

	END
RO