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\begin{document}
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\title{DLXsim -- A Simulator for DLX}
\author{Larry B. Hostetler \and Brian Mirtich}
\maketitle

\section{Introduction}

Our project involved writing a simulator ({\dlxsim}) for the DLX
instruction set (as described in {\em Computer Architecture, A
Quantitative Approach} by Hennessy and Patterson).
\dlxsim\ is an interactive program that loads DLX assembly programs
and simulates the operation of a DLX computer on those programs,
allowing both single-stepping and continuous execution through the DLX
code.  \dlxsim\ also provides the user with commands to set
breakpoints, view and modify memory and registers, and print statistics on the
execution of the program allowing the user to collect various
information on the run-time properties of a program.  We expect that a
major use for this tool will be in association with future CS 252
classes to aid in the understanding of this instruction set.

A complete overview of the interface provided by the simulator can be
found in the user manual for \dlxsim, which has been included after
this section.  Later in this paper, a few sample runs of the simulator
will also be given.

We decided that since the MIPS instruction set has many similarities
with DLX, and a good MIPS simulator (available from Ousterhaut)
already exists, it would be a better use of our time to modify that
simulator to handle the DLX description.  This simulator was built on
top of the Tcl interface, providing a programming type environment for
the user as well.

The main problem we encountered when rewriting the simulator was that
there are a couple of fundamental differences between the DLX and MIPS
architectures.  Following is a list of the main differences we
identified between the two architectures.

\begin{itemize}

\item In MIPS, branch and jump offsets are stored as the number of
words, where DLX stores the number of bytes.  This has the effect of
allowing jumps on MIPS to go four times as far.

\item MIPS jumps have a non-obvious approach to determining the
destination address: the bits in the offset part of the instruction
simply replace the lower bits in the program counter.  DLX chooses a
more conventional approach in that the offset is sign extended, and
then added to the program counter.

\item In the MIPS architecture, conditional branches are based on the
result of a comparison between any two registers.  DLX has only two
main conditional branch operations which branch on whether a register
is zero or non-zero.

\item DLX provides load interlocks, while the MIPS 2000 does not.

\item MIPS 2000 provides instructions for unaligned accesses to
memory, while DLX does not.

\item The result of a MIPS multiply or divide ends up in two special
registers (HI and LO) allowing 64 bit results; the result of a DLX
multiply is placed in the chosen general purpose register, and must
therefore fit into 32 bits.

\end{itemize}

Because of the large number of similarities between DLX and MIPS, we
based our opcodes on those used by the MIPS machine (where MIPS had
equivalent instructions).  Where DLX had instructions with no MIPS
equivalent, we grouped such similar DLX instructions and assigned to
them blocks of unused opcodes.  Below, you will find the opcode
numbers used for the DLX instructions.  Register-register
instructions have the {\bf special} opcode, and the instruction is
specified in the lower six bits of the instruction word.  Similarly,
floating point instructions have the {\bf fparith} opcode, and the
actual instruction is again found in the lower six bits of the word.

\vspace{.25in}

\vbox{
\begin{center}
Main opcodes
\end{center}

\begin{tabular}{r|c|c|c|c|c|c|c|c|}
 & \$00 & \$01 & \$02 & \$03 & \$04 & \$05 & \$06 & \$07 \\ \hline
\$00 & SPECIAL & FPARITH & J & JAL & BEQZ & BNEZ & BFPT & BFPF \\ \hline
\$08 & ADDI & ADDUI & SUBI & SUBUI & ANDI & ORI & XORI & LHI \\ \hline
\$10 & RFE & TRAP & JR & JALR & & & & \\ \hline
\$18 & SEQI & SNEI & SLTI & SGTI & SLEI & SGEI & & \\ \hline
\$20 & LB & LH & & LW & LBU & LHU & LF & LD \\ \hline
\$28 & SB & SH & & SW & & & SF & SD \\ \hline
\$30 & SEQUI & SNEUI & SLTUI & SGTUI & SLEUI & SGEUI & & \\ \hline
\end{tabular}
}

\vspace{.25in}

\vbox{
\begin{center}
Special opcodes (Main opcode = \$00)
\end{center}

\begin{tabular}{r|c|c|c|c|c|c|c|c|}
 & \$00 & \$01 & \$02 & \$03 & \$04 & \$05 & \$06 & \$07 \\ \hline
\$00 & SLLI & & SRLI & SRAI & SLL & & SRL & SRA \\ \hline
\$08 & & & & & TRAP & & & \\ \hline
\$10 & SEQU & SNEU & SLTU & SGTU & SLEU & SGEU & & \\ \hline
\$18 & MULT & MULTU & DIV & DIVU & & & & \\ \hline
\$20 & ADD & ADDU & SUB & SUBU & AND & OR & XOR & \\ \hline
\$28 & SEQ & SNE & SLT & SGT & SLE & SGE & & \\ \hline
\$30 & MOVI2S & MOVS2I & MOVF & MOVD & MOVFP2I & MOVI2FP & & \\ \hline
\end{tabular}
}

\vspace{.25in}

\vbox{
\begin{center}
Floating Point opcodes (Main opcode = \$01)
\end{center}

\begin{tabular}{r|c|c|c|c|c|c|c|c|}
 & \$00 & \$01 & \$02 & \$03 & \$04 & \$05 & \$06 & \$07 \\ \hline
\$00 & ADDF & SUBF & MULTF & DIVF & ADDD & SUBD & MULTD & DIVD \\ \hline
\$08 & CVTF2D & CVTF2I & CVTD2F & CVTD2I & CVTI2F & CVTI2D & & \\ \hline
\$10 & EQF & NEF & LTF & GTF & LEF & GEF & & \\ \hline
\$18 & EQD & NED & LTD & GTD & LED & GED & & \\ \hline
\end{tabular}
}

\vspace{.5in}

The manual entry for \dlxsim\ follows.

\newpage

\markboth{DLXSIM \hfill User Commands \hfill Page\ }{DLXSIM \hfill User Commands \hfill Page\ }
\pagestyle{myheadings}

\input{dlxsim}

\newpage

\pagestyle{plain}

\input{report2}

\end{document}