include	"SNES.i"

	incdir	"!includes:OS3.0"
	include	"intuition/intuition.i"

	incdir	"!includes:"
	include	"LVO/intuition_lib.i"
	include	"LVO/graphics_lib.i"
	include	"LVO/dos_lib.i"

	section	code,code

	move.l	#-1,d0	* prevent execution
	rts

HWR_GetWord
* * * * * * * * * * * * * * * * * * * * * * * * *
* Gets a hardware-register.			*
*						*
* IN:	d0 - Pointer to hardware register.(word)*
*						*
* OUT:	d0 - Word.				*
*						*
* * * * * * * * * * * * * * * * * * * * * * * * *

	move.l	d0,d2
	jsr	HWR_GetByte
	rol.w	#8,d3
	move.w	d0,d3
	move.l	d2,d0
	jsr	HWR_GetByte
	move.b	d0,d3
	move.w	d3,d0

	rts


HWR_SetWord
* * * * * * * * * * * * * * * * * * * * * * * * *
* Writes a word to a hardware-register.		*
*						*
* IN:	d0 - Pointer to hardware register.(word)*
*	d1 - word to write.			*
*						*
* * * * * * * * * * * * * * * * * * * * * * * * *

	move.l	d0,d2
	move.l	d1,d3
	jsr	HWR_SetByte
	move.l	d2,d0
	add.l	#1,d0
	move.l	d3,d1
	lsr.w	#8,d1
	jmp	HWR_SetByte

HWR_GetByte
* * * * * * * * * * * * * * * * * * * * * * * * *
* Gets a hardware-register.			*
*						*
* IN:	d0 - Pointer to hardware register.(word)*
*						*
* OUT:	d0 - Byte.				*
*						*
* * * * * * * * * * * * * * * * * * * * * * * * *

	ror.w	#8,d0

	cmp.b	#$21,d0
	beq	.gr_21h

	cmp.b	#$42,d0
	beq	.gr_42h

.gr_Fail
	rts				;no read-regs at $43xx..

.gr_21h
	rol.w	#8,d0
	and.l	#$000000ff,d0

	cmp.w	#$83,d0
	bgt	.gr_Fail

	lea.l	prg_21hGetJumpTable,a1
	move.l	(a1,d0*4),a1
	jmp	(a1)

.gr_42h
	rol.w	#8,d0
	and.l	#$000000ff,d0

	cmp.w	#$1f,d0
	bgt	.gr_Fail

	lea.l	prg_42hGetJumpTable,a1
	move.l	(a1,d0*4),a1
	jsr	(a1)

	and.l	#$ff,d0
	rts

HWR_SetByte
* * * * * * * * * * * * * * * * * * * * * * * * *
* Writes a byte to a hardware-register.		*
*						*
* IN:	d0 - Pointer to hardware register.(word)*
*	d1 - byte to write.			*
*						*
* * * * * * * * * * * * * * * * * * * * * * * * *

	and.l	#$ff,d1
	ror.w	#8,d0

	cmp.b	#$21,d0
	beq	.sr_21h

	cmp.b	#$42,d0
	beq	.sr_42h

	cmp.b	#$43,d0
	beq	.sr_43h

.sr_Fail
	rts

.sr_21h
	rol.w	#8,d0
	and.l	#$000000ff,d0

	cmp.w	#$83,d0
	bgt	.sr_Fail

	lea.l	prg_21hSetJumpTable,a1
	move.l	(a1,d0*4),a1
	jmp	(a1)

.sr_42h
	rol.w	#8,d0
	and.l	#$000000ff,d0

	cmp.w	#$1F,d0
	bgt	.sr_Fail

	lea.l	prg_42hSetJumpTable,a1
	move.l	(a1,d0*4),a1
	jmp	(a1)

.sr_43h
	rol.w	#8,d0
	and.l	#$000000ff,d0

	cmp.w	#$7A,d0
	bgt	.sr_Fail

	lea.l	prg_43hSetJumpTable,a1
	move.l	(a1,d0*4),a1
	jmp	(a1)

	*** Hardware jump-tables ***

prg_21hGetJumpTable
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	get_MPYL		;2134
	dc.l	get_MPYM		;2135
	dc.l	get_MPYH		;2136
	dc.l	get_SLHV		;2137
	dc.l	get_OAMDATAREAD		;2138
	dc.l	get_VMDATALREAD		;2139
	dc.l	get_VMDATAHREAD		;213A
	dc.l	get_CGDATAREAD		;213B
	dc.l	get_OPHCT		;213C
	dc.l	get_OPVCT		;213D
	dc.l	get_STAT77		;213E
	dc.l	get_STAT78		;213F
	dc.l	get_APUI00		;2140
	dc.l	get_APUI01		;2141
	dc.l	get_APUI02		;2142
	dc.l	get_APUI03		;2143
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	get_WMDATA		;2180
	dc.l	get_WMADDL		;2181
	dc.l	get_WMADDM		;2182
	dc.l	get_WMADDH		;2183

HWFail
	rts

get_MPYL	;Multiplication result register (low)
	rts

get_MPYM	;Multiplication result register (middle)
	rts

get_MPYH	;Multiplication result register (high)
	rts

get_SLHV	;Software latch for horizontal/vertical counter
	rts

get_OAMDATAREAD	;Read data from OAM
	rts

get_VMDATALREAD	;Read data from VRAM
	rts

get_VMDATAHREAD	;Read data from VRAM
	rts

get_CGDATAREAD	;Read data from CG-RAM (colour)
	rts

get_OPHCT	;Horizontal scanline location
	rts

get_OPVCT	;Vertical scanline location
	rts

get_STAT77	;PPU status flag & version number
	rts

get_STAT78	;PPU status flag & version number
	rts

get_APUI00	;Sound register

	;APU skipper for APUI00
	;Should take care of most
	;sound-upload lockups

	move.l	SHW_APU00Count(a6),d1

.Attempt1
	cmp.l	#0,d1
	bne	.Attempt2
	move.w	d7,d0	;return AL
	add.l	#1,SHW_APU00Count(a6)
	move.l	#0,SHW_APU01Count(a6)
	rts

.Attempt2
	cmp.l	#1,d1
	bne	.Attempt3
	move.w	d6,d0	;return XL
	add.l	#1,SHW_APU00Count(a6)
	move.l	#1,SHW_APU01Count(a6)
	rts

.Attempt3
	cmp.l	#2,d1
	bne	.Attempt4
	move.w	d6,d0
	swap	d0	;return YL
	add.l	#1,SHW_APU00Count(a6)
	move.l	#2,SHW_APU01Count(a6)
	rts

.Attempt4
	cmp.l	#3,d1
	bne	.Attempt5
	clr.l	d0
	add.l	#1,SHW_APU00Count(a6)
	rts

.Attempt5
	cmp.l	#4,d1
	bne	.Attempt6
	move.l	#$ff,d0
	add.l	#1,SHW_APU00Count(a6)
	rts

.Attempt6
	cmp.l	#5,d1
	bne	.Attempt7
	move.l	#$55,d0
	add.l	#1,SHW_APU00Count(a6)
	rts

.Attempt7
	cmp.l	#6,d1
	bne	.Attempt8
	move.l	#$01,d0
	add.l	#1,SHW_APU00Count(a6)
	rts

.Attempt8
	cmp.l	#7,d1
	bne	.Attempt9
	move.l	#$aa,d0
	add.l	#1,SHW_APU00Count(a6)
	move.l	#6,SHW_APU01Count(a6)
	rts

.Attempt9
	cmp.l	#8,d1
	bne	.Attempt10
	move.l	SHW_APU00Hold(a6),d0
	add.l	#1,SHW_APU00Count(a6)
	rts

.Attempt10
	move.l	SHW_APU00Fix(a6),d1
	move.l	d1,d0
	add.l	#1,d1
	move.l	d1,SHW_APU00Fix(a6)

	move.l	#$b,SHW_APU01Count(a6)

	tst.l	d1
	beq	.ResetSkipper00

	rts

.ResetSkipper00

	clr.l	SHW_APU00Count(a6)
	add.l	#1,SHW_APU01Fix(a6)
	clr.l	SHW_APU01Count(a6)

	rts


get_APUI01	;Sound register

	;APU skipper for APU01

	move.l	SHW_APU01Count(a6),d1

.Attempt1
	cmp.l	#0,d1
	bne	.Attempt2
	move.w	d7,d0
	lsr.w	#8,d0	;return AH
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt2
	cmp.l	#1,d1
	bne	.Attempt3
	move.w	d6,d0
	lsr.w	#8,d0	;return XH
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt3
	cmp.l	#2,d1
	bne	.Attempt4
	move.l	d6,d0
	swap	d0
	lsr.w	#8,d0	;return YH
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt4
	cmp.l	#3,d1
	bne	.Attempt5
	move.w	d7,d0	;return AL
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt5
	cmp.l	#4,d1
	bne	.Attempt6
	move.w	d6,d0	;return XL
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt6
	cmp.l	#5,d1
	bne	.Attempt7
	move.l	d6,d0
	swap	d0	;return YL
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt7
	cmp.l	#6,d1
	bne	.Attempt8
	move.l	#$bb,d0
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt8
	cmp.l	#7,d1
	bne	.Attempt9
	move.l	#0,d0
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt9
	cmp.l	#8,d1
	bne	.Attempt10
	move.l	#$ff,d0
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt10
	cmp.l	#9,d1
	bne	.Attempt11
	move.l	#$55,d0
	add.l	#1,SHW_APU01Count(a6)
	rts

.Attempt11
	cmp.l	#$a,d1
	bne	.Attempt12
	move.l	SHW_APU01Hold(a6),d0
	move.l	#0,SHW_APU01Count(a6)
	rts

.Attempt12
	move.l	SHW_APU01Fix(a6),d0
	rts


get_APUI02	;Sound register

	;APU skipper for APUI02

	move.l	SHW_APU02Count(a6),d1

.Attempt1
	cmp.l	#0,d1
	bne	.Attempt2
	move.w	d7,d0	;return AL
	add.l	#1,SHW_APU02Count(a6)
	move.l	#0,SHW_APU03Count(a6)
	rts

.Attempt2
	cmp.l	#1,d1
	bne	.Attempt3
	move.w	d6,d0	;return XL
	add.l	#1,SHW_APU02Count(a6)
	move.l	#1,SHW_APU03Count(a6)
	rts

.Attempt3
	cmp.l	#2,d1
	bne	.Attempt4
	move.w	d6,d0
	swap	d0	;return YL
	add.l	#1,SHW_APU02Count(a6)
	move.l	#2,SHW_APU03Count(a6)
	rts

.Attempt4
	cmp.l	#3,d1
	bne	.Attempt5
	clr.l	d0
	add.l	#1,SHW_APU02Count(a6)
	rts

.Attempt5
	cmp.l	#4,d1
	bne	.Attempt6
	move.l	#$ff,d0
	add.l	#1,SHW_APU02Count(a6)
	rts

.Attempt6
	cmp.l	#5,d1
	bne	.Attempt7
	move.l	#$55,d0
	add.l	#1,SHW_APU02Count(a6)
	rts

.Attempt7
	cmp.l	#6,d1
	bne	.Attempt8
	move.l	#$aa,d0
	add.l	#1,SHW_APU02Count(a6)
	move.l	#6,SHW_APU03Count(a6)
	rts

.Attempt8
	move.l	SHW_APU02Hold(a6),d0
	move.l	#0,SHW_APU02Count(a6)
	rts

get_APUI03	;Sound register

	;APU skipper for APU03

	move.l	SHW_APU03Count(a6),d1

.Attempt1
	cmp.l	#0,d1
	bne	.Attempt2
	move.w	d7,d0
	lsr.w	#8,d0	;return AH
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt2
	cmp.l	#1,d1
	bne	.Attempt3
	move.w	d6,d0
	lsr.w	#8,d0	;return XH
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt3
	cmp.l	#2,d1
	bne	.Attempt4
	move.l	d6,d0
	swap	d0
	lsr.w	#8,d0	;return YH
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt4
	cmp.l	#3,d1
	bne	.Attempt5
	move.w	d7,d0	;return AL
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt5
	cmp.l	#4,d1
	bne	.Attempt6
	move.w	d6,d0	;return XL
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt6
	cmp.l	#5,d1
	bne	.Attempt7
	move.l	d6,d0
	swap	d0	;return YL
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt7
	cmp.l	#6,d1
	bne	.Attempt8
	move.l	#$bb,d0
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt8
	cmp.l	#7,d1
	bne	.Attempt9
	move.l	#0,d0
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt9
	cmp.l	#8,d1
	bne	.Attempt10
	move.l	#$ff,d0
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt10
	cmp.l	#9,d1
	bne	.Attempt11
	move.l	#$55,d0
	add.l	#1,SHW_APU03Count(a6)
	rts

.Attempt11
	move.l	SHW_APU03Hold(a6),d0
	move.l	#0,SHW_APU03Count(a6)
	rts

get_WMDATA	;Read/write WRAM register
	rts

get_WMADDL	;WRAM data register (low byte)
	rts

get_WMADDM	;WRAM data register (middle byte)
	rts

get_WMADDH	;WRAM data register (high byte)
	rts

prg_21hSetJumpTable
	dc.l	set_INIDISP		;2100
	dc.l	set_OBSEL		;2101
	dc.l	set_OAMADDL		;2102
	dc.l	set_OAMADDH		;2103
	dc.l	set_OAMDATA		;2104
	dc.l	set_BGMODE		;2105
	dc.l	set_MOSAIC		;2106
	dc.l	set_BG1SC		;2107
	dc.l	set_BG2SC		;2108
	dc.l	set_BG3SC		;2109
	dc.l	set_BG4SC		;210A
	dc.l	set_BG12NBA		;210B
	dc.l	set_BG34NBA		;210C
	dc.l	set_BG1HOFS		;210D
	dc.l	set_BG1VOFS		;210E
	dc.l	set_BG2HOFS		;210F
	dc.l	set_BG2VOFS		;2110
	dc.l	set_BG3HOFS		;2111
	dc.l	set_BG3VOFS		;2112
	dc.l	set_BG4HOFS		;2113
	dc.l	set_BG4VOFS		;2114
	dc.l	set_VMAIN		;2115
	dc.l	set_VMADDL		;2116
	dc.l	set_VMADDH		;2117
	dc.l	set_VMDATAL		;2118
	dc.l	set_VMDATAH		;2119
	dc.l	set_M7SEL		;211A
	dc.l	set_M7A		;211B
	dc.l	set_M7B		;211C
	dc.l	set_M7C		;211D
	dc.l	set_M7D		;211E
	dc.l	set_M7X		;211F
	dc.l	set_M7Y		;2120
	dc.l	set_CGADD		;2121
	dc.l	set_CGDATA		;2122
	dc.l	set_W12SEL		;2123
	dc.l	set_W34SEL		;2124
	dc.l	set_WOBJSEL		;2125
	dc.l	set_WH0		;2126
	dc.l	set_WH1		;2127
	dc.l	set_WH2		;2128
	dc.l	set_WH3		;2129
	dc.l	set_WBGLOG		;212A
	dc.l	set_WOBJLOG		;212B
	dc.l	set_TM		;212C
	dc.l	set_TD		;212D
	dc.l	set_TMW		;212E
	dc.l	set_TSW		;212F
	dc.l	set_CGWSEL		;2130
	dc.l	set_CGADSUB		;2131
	dc.l	set_COLDATA		;2132
	dc.l	set_SETINI		;2133
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_APUI00		;2140
	dc.l	set_APUI01		;2141
	dc.l	set_APUI02		;2142
	dc.l	set_APUI03		;2143
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_WMDATA		;2180
	dc.l	set_WMADDL		;2181
	dc.l	set_WMADDM		;2182
	dc.l	set_WMADDH		;2183


set_INIDISP	;Screen display register

	move.l	d2,-(sp)

	clr.l	d0
	btst.b	#7,d1
	seq	d0
	move.l	SHW_ScreenEnable(a6),d2
	move.l	d0,SHW_ScreenEnable(a6)

	cmp.l	d0,d2
	beq	.NoScreenChange

	st.l	SHW_ScreenChange(a6)		;notify of change

.NoScreenChange

	and.l	#$f,d1
	move.l	d1,SHW_ScreenBrightness(a6)
	st.l	SHW_PaletteChange(a6)

	move.l	(sp)+,d2

	rts

set_OBSEL	;OAM size register
	rts

set_OAMADDL	;OAM address register
	rts

set_OAMADDH	;OAM address register

	rts

set_OAMDATA	;OAM data register
	rts

set_BGMODE	;Screen mode register

	;implement e: Highest priority for BG3 in MODE 1.

	* set tile-sizes

	move.l	d1,d0

	and.l	#$f0,d1
	lsr.l	#4,d1
	move.l	d1,SHW_BGTileSize(a6)

	* set screen mode

	move.l	d0,d1
	and.l	#$7,d1
	move.l	d1,SHW_ScreenMode(a6)

	st.l	SHW_ScreenChange(a6)

	rts

set_MOSAIC	;Screen pixelation register

	move.l	d1,SHW_ScreenPixelation(a6)
	st.l	SHW_ScreenChange(a6)

	rts

set_BG1SC	;BG1 VRAM location register

	move.l	d1,d0
	and.l	#3,d0
	move.w	d0,SHW_BG1SCSize

	and.b	#$fc,d1
	lsl.w	#8,d1
	move.w	d1,SHW_BG1SCAddress(a6)

	rts

set_BG2SC	;BG2 VRAM location register

	move.l	d1,d0
	and.l	#3,d0
	move.w	d0,SHW_BG2SCSize

	and.b	#$fc,d1
	lsl.w	#8,d1
	move.w	d1,SHW_BG2SCAddress(a6)

	rts

set_BG3SC	;BG3 VRAM location register

	move.l	d1,d0
	and.l	#3,d0
	move.w	d0,SHW_BG3SCSize

	and.b	#$fc,d1
	lsl.w	#8,d1
	move.w	d1,SHW_BG3SCAddress(a6)

	rts

set_BG4SC	;BG4 VRAM location register

	move.l	d1,d0
	and.l	#3,d0
	move.w	d0,SHW_BG4SCSize

	and.b	#$fc,d1
	lsl.w	#8,d1
	move.w	d1,SHW_BG4SCAddress(a6)

	rts

set_BG12NBA	;BG1 & BG2 VRAM location register

	move.b	d1,d0
	lsl.w	#8,d0
	lsl.w	#4,d0
	move.w	d0,SHW_BG1TileAddress(a6)

	lsl.w	#8,d1
	and.w	#$f000,d1
	move.w	d1,SHW_BG2TileAddress(a6)

	rts

set_BG34NBA	;BG3 & BG4 VRAM location register

	move.b	d1,d0
	lsl.w	#8,d0
	lsl.w	#4,d0
	move.w	d0,SHW_BG3TileAddress(a6)

	lsl.w	#8,d1
	and.w	#$f000,d1
	move.w	d1,SHW_BG4TileAddress(a6)

	rts

set_BG1HOFS	;BG1 horizontal scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG1HorizScroll

	rts

set_BG1VOFS	;BG1 vertical scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG1VertScroll

	rts

set_BG2HOFS	;BG2 horizontal scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG2HorizScroll

	rts

set_BG2VOFS	;BG3 vertical scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG2VertScroll

	rts

set_BG3HOFS	;BG3 horizontal scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG3HorizScroll

	rts

set_BG3VOFS	;BG3 vertical scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG3VertScroll

	rts

set_BG4HOFS	;BG4 horizontal scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG4HorizScroll

	rts

set_BG4VOFS	;BG4 vertical scroll register

	st.l	SHW_ScreenChange(a6)

	DOUBLEWRITE	BG4VertScroll

	rts

set_VMAIN	;Video port control

	clr.l	d0

	btst.b	#7,d1
	sne	d0

	move.l	d0,SHW_VRAMStoreMode(a6)

	rts

set_VMADDL	;Video port address

	move.b	d1,SHW_VRAMAddrLow(a6)

	rts

set_VMADDH	;Video port address

	move.b	d1,SHW_VRAMAddrHigh(a6)

	move.w	SHW_VRAMAddress(a6),d0
	lsl.w	#1,d0
	move.w	d0,SHW_VRAMAddress(a6)

	rts

set_VMDATAL	;Video port data

	move.b	d1,SHW_VRAMDataLow(a6)

	tst.l	SHW_VRAMStoreMode(a6)
	bne	.SkipWrite

	clr.l	d1
	move.w	SHW_VRAMAddress(a6),d1
	move.l	ptr_SNESVRam,a1
	add.l	d1,a1

	move.w	SHW_VRAMData(a6),(a1)

	add.l	#2,d1
	move.w	d1,SHW_VRAMAddress(a6)

	st.l	SHW_ScreenChange(a6)

.SkipWrite

	rts

set_VMDATAH	;Video port data

	move.b	d1,SHW_VRAMDataHigh(a6)

	tst.l	SHW_VRAMStoreMode(a6)
	beq	.SkipWrite

	clr.l	d1
	move.w	SHW_VRAMAddress(a6),d1
	move.l	ptr_SNESVRam,a1
	add.l	d1,a1

	move.w	SHW_VRAMData(a6),(a1)

	add.l	#2,d1
	move.w	d1,SHW_VRAMAddress(a6)

	st.l	SHW_ScreenChange(a6)

.SkipWrite

	rts

set_M7SEL	;MODE7 settings register
	rts

set_M7A	;COS (COSINE) rotate angle / X Expansion
	rts

set_M7B	;SIN (SIN) rotate angle / X Expansion
	rts

set_M7C	;SIN (SIN) rotate angle / Y Expansion
	rts

set_M7D	;COS (COSINE) rotate angle / Y Expansion
	rts

set_M7X	;Center position X (13-bit data only)
	rts

set_M7Y	;Center position Y (13-bit data only)
	rts

set_CGADD	;Colour # (or palette) selection register

	move.l	d1,SHW_ColourSelect(a6)

	rts

set_CGDATA	;Colour data register

	tst.l	SHW_ColourStore(a6)
	bmi	.first_CGDATA

	* store color in CGRAM

	lea.l	SHW_ColorRAM(a6),a1

	clr.l	d0
	move.l	SHW_ColourSelect(a6),d0
	lsl.l	#1,d0
	add.l	d0,a1

	move.l	SHW_ColourStore(a6),d0
	rol.w	#8,d1
	or.w	d1,d0

	move.w	d0,(a1)

	* initialize for next color

	add.l	#1,SHW_ColourSelect(a6)
	move.l	#-1,SHW_ColourStore(a6)

	* notify gfx-engine of change in palette

	st.l	SHW_PaletteChange(a6)

	rts

.first_CGDATA

	move.l	d1,SHW_ColourStore(a6)
	rts

set_W12SEL	;Window mask settings register
	rts

set_W34SEL	;Window mask settings register
	rts

set_WOBJSEL	;Window mask settings register
	rts

set_WH0	;Window 1 left position register
	rts

set_WH1	;Window 1 right position register
	rts

set_WH2	;Window 2 left position register
	rts

set_WH3	;Window 2 right position register
	rts

set_WBGLOG	;Mask logic settings for Window 1 & 2 per screen
	rts

set_WOBJLOG	;Mask logic settings for Colour Windows & OBJ Windows
	rts

set_TM	;Main screen designation

	and.l	#$f,d1
	move.l	d1,SHW_BGEnable(a6)

	rts

set_TD	;Sub-screen designation
	rts

set_TMW	;Window mask main screen designation register
	rts

set_TSW	;Window mask sub screen designation register
	rts

set_CGWSEL	;Fixed color addition or screen addition register
	rts

set_CGADSUB	;Addition/subtraction for screens, BGs, & OBJs
	rts

set_COLDATA	;Fixed colour data for fixed colour +/-
	rts

set_SETINI	;Screen mode/video select register

	move.l	d1,SHW_ScreenSettings(a6)

	st.l	SHW_ScreenChange(a6)

	rts

set_APUI00	;Sound register

	move.l	d1,SHW_APU00Hold(a6)
	rts

set_APUI01	;Sound register

	move.l	d1,SHW_APU01Hold(a6)
	move.l	#0,SHW_APU01Count(a6)
	rts

set_APUI02	;Sound register

	move.l	d1,SHW_APU02Hold(a6)
	move.l	#0,SHW_APU02Count(a6)
	rts

set_APUI03	;Sound register

	move.l	d1,SHW_APU03Hold(a6)
	move.l	#0,SHW_APU03Count(a6)
	rts

set_WMDATA	;Read/write WRAM register
	rts

set_WMADDL	;WRAM data register (low byte)
	rts

set_WMADDM	;WRAM data register (middle byte)
	rts

set_WMADDH	;WRAM data register (high byte)
	rts

prg_42hGetJumpTable
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	get_RDNMI		;4210
	dc.l	get_TIMEUP		;4211
	dc.l	get_HVBJOY		;4212
	dc.l	get_RDIO		;4213
	dc.l	get_RDDIVL		;4214
	dc.l	get_RDDIVH		;4215
	dc.l	get_RDMPYL		;4216
	dc.l	get_RDMPYH		;4217
	dc.l	get_JOY1L		;4218
	dc.l	get_JOY1H		;4219
	dc.l	get_JOY2L		;421A
	dc.l	get_JOY2H		;421B
	dc.l	get_JOY3L		;421C
	dc.l	get_JOY3H		;421D
	dc.l	get_JOY4L		;421E
	dc.l	get_JOY4H		;421F

get_RDNMI	;NMI register

	tst.l	SHW_ScreenEnable(a6)
	beq	.special_DisplayOff

	tst.l	prg_FrameSkip
	bne	.special_FrameSkip

	move.l	SHW_ReadNMI(a6),d0
	clr.l	SHW_ReadNMI(a6)

	sub.l	#1,SHW_NMIAccess(a6)
	bpl	.NoVBLOccur

	lea.l	prg_ConfigBuffer,a1
	tst.l	CFG_FastVBL(a1)
	beq	.NoVBLOccur

	move.l	#-1,d5

.NoVBLOccur

	rts

.special_FrameSkip

	subq.l	#1,prg_FrameSkip

	move.l	#$80,d0

	rts

.special_DisplayOff

	not.l	SHW_DisplayOffCount(a6)
	beq	.no_Update

	move.l	#$80,d0
	rts

.no_Update

	move.l	#$0,d0
	rts

get_TIMEUP	;Video IRQ register
	rts

get_HVBJOY	;Status register
	move.l	SHW_JoypadEnabled(a6),d0
	move.l	#0,d0
	rts

get_RDIO	;Programmable I/O port (in-port)
	rts

get_RDDIVL	;Quotient of divide result
	rts

get_RDDIVH	;Quotient of divide result
	rts

get_RDMPYL	;Multiplication or divide result
	move.b	SHW_MultiplyLow(a6),d0
	rts

get_RDMPYH	;Multiplication or divide result
	move.b	SHW_MultiplyHigh(a6),d0
	rts

get_JOY1L	;Joypad #1 status register
	clr.l	d0
	move.b	SHW_Joypad1DataLow(a6),d0
	rts

get_JOY1H	;Joypad #1 status register
	clr.l	d0
	move.b	SHW_Joypad1DataHigh(a6),d0
	rts

get_JOY2L	;Joypad #2 status register
	move.l	#0,d0		;no presses yet
	rts

get_JOY2H	;Joypad #2 status register
	move.l	#0,d0		;no presses yet
	rts

get_JOY3L	;Joypad #3 status register
	move.l	#0,d0		;no presses yet
	rts

get_JOY3H	;Joypad #3 status register
	move.l	#0,d0		;no presses yet
	rts

get_JOY4L	;Joypad #4 status register
	move.l	#0,d0		;no presses yet
	rts

get_JOY4H	;Joypad #4 status register
	move.l	#0,d0		;no presses yet
	rts

prg_42hSetJumpTable
	dc.l	set_NMITIMEN		;4200
	dc.l	set_WRIO		;4201
	dc.l	set_WRMPYA		;4202
	dc.l	set_WRMPYB		;4203
	dc.l	set_WRDIVL		;4204
	dc.l	set_WRDIVH		;4205
	dc.l	set_WRDIVB		;4206
	dc.l	set_HTIMEL		;4207
	dc.l	set_HTIMEH		;4208
	dc.l	set_VTIMEL		;4209
	dc.l	set_VTIMEH		;420A
	dc.l	set_MDMAEN		;420B
	dc.l	set_HDMAEN		;420C
	dc.l	set_MEMSEL		;420D
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_TIMEUP		;4211
	dc.l	set_HVBJOY		;4212
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail

set_NMITIMEN	;Counter enable

	* Enable or disable joypad

	move.l	d1,d0
	and.l	#$01,d0
	move.l	d0,SHW_JoypadEnabled(a6)

	rts

set_WRIO	;Programmable I/O port (out-port)
	rts

set_WRMPYA	;Multiplicand 'A'
	move.b	d1,SHW_MultiplyOperatorA(a6)
	rts

set_WRMPYB	;Multiplier 'B'
	move.b	d1,SHW_MultiplyOperatorB(a6)	;not necessary

	;perform A(8b)*B(8b) = C((16b)

	clr.l	d0
	move.b	SHW_MultiplyOperatorA(a6),d0
	mulu.w	d0,d1
	move.w	d1,SHW_MultiplyResult(a6)

	rts

set_WRDIVL	;Dividend C
	rts

set_WRDIVH	;Dividend C
	rts

set_WRDIVB	;Divisor B
	rts

set_HTIMEL	;Video horizontal IRQ beam position/pointer
	rts

set_HTIMEH	;Video horizontal IRQ beam position/pointer
	rts

set_VTIMEL	;Video vertical IRQ beam position/pointer
	rts

set_VTIMEH	;Video vertical IRQ beam position/pointer
	rts

set_MDMAEN	;DMA enable register

	movem.l	d0-a6,-(sp)

	btst.b	#0,d1
	beq	.no_DMA0

	lea.l	SHW_DMA0(a6),a1
	bsr	.ExecuteDMA

.no_DMA0

	btst.b	#1,d1
	beq	.no_DMA1

	lea.l	SHW_DMA1(a6),a1
	bsr	.ExecuteDMA

.no_DMA1

	btst.b	#2,d1
	beq	.no_DMA2

	lea.l	SHW_DMA2(a6),a1
	bsr	.ExecuteDMA

.no_DMA2

	btst.b	#3,d1
	beq	.no_DMA3

	lea.l	SHW_DMA3(a6),a1
	bsr	.ExecuteDMA

.no_DMA3

	btst.b	#4,d1
	beq	.no_DMA4

	lea.l	SHW_DMA4(a6),a1
	bsr	.ExecuteDMA

.no_DMA4

	btst.b	#5,d1
	beq	.no_DMA5

	lea.l	SHW_DMA5(a6),a1
	bsr	.ExecuteDMA

.no_DMA5

	btst.b	#6,d1
	beq	.no_DMA6

	lea.l	SHW_DMA6(a6),a1
	bsr	.ExecuteDMA

.no_DMA6

	btst.b	#7,d1
	beq	.no_DMA7

	lea.l	SHW_DMA7(a6),a1
	bsr	.ExecuteDMA

.no_DMA7

	movem.l	(sp)+,d0-a6
	rts

.ExecuteDMA
	movem.l	d0-a6,-(sp)

	*** TODO VERY SOON: rewrite ALL dma-code ***

	;WARNING! This DMA transfer is VERY beta!

	move.l	a1,a5

	move.l	DMA_MemAddr(a5),d6

	clr.l	d5
	move.w	#$2100,d5
	move.b	DMA_HWAddr(a5),d5

	cmp.b	#$18,d5			;MEM -> VRAM
	bne	.no_VRAM

	*** VRAM START

	;calculate size of copy and clip if overriding

	clr.l	d7
	move.w	DMA_Size(a5),d7
	clr.l	d0
	move.w	SHW_VRAMAddress(a6),d0

	add.l	d7,d0
	cmp.l	#65536,d0
	blt.s	.DMA_noclip

	sub.l	#65535,d0
	sub.l	d0,d7

.DMA_noclip

	;calculate absolute amiga adresses

	move.l	DMA_MemAddr(a5),d0
	jsr	EMU_GetSNESAddress
	move.l	d0,a2

	clr.l	d0
	move.w	SHW_VRAMAddress(a6),d0
	add.l	ptr_SNESVRam,d0
	move.l	d0,a3

	move.l	d7,d6

	subq.l	#1,d7
.DMATransfer

	move.b	(a2)+,(a3)+

	dbra	d7,.DMATransfer

	add.w	d6,SHW_VRAMAddress(a6)

	st.l	SHW_ScreenChange(a6)

	bra	.no_DMA

	*** VRAM END

.no_VRAM

	cmp.b	#$22,d5			;MEM -> CGRAM
	bne	.no_CGRAM

	*** CGRAM START

	;calculate size of copy and clip if overriding

	clr.l	d7
	move.w	DMA_Size(a5),d7
	move.l	SHW_ColourSelect(a6),d0
	lsl.l	#1,d0

	add.l	d7,d0
	cmp.l	#512,d0
	blt.s	.DMA_noclip_CGRAM

	sub.l	#512,d0
	sub.l	d0,d7

.DMA_noclip_CGRAM

	;calculate absolute amiga adresses

	move.l	DMA_MemAddr(a5),d0
	jsr	EMU_GetSNESAddress
	move.l	d0,a2

	lea.l	SHW_ColorRAM(a6),a3
	move.l	SHW_ColourSelect(a6),d0
	lsl.l	#1,d0
	add.l	d0,a3

	move.l	d7,d6

	subq.l	#1,d7
.DMATransfer_CGRAM

	move.b	(a2)+,(a3)+

	dbra	d7,.DMATransfer_CGRAM

	lsr.l	#1,d6
	add.w	d6,SHW_ColourSelect(a6)

	st.l	SHW_PaletteChange(a6)

	bra	.no_DMA

	*** CGRAM END

.no_CGRAM

.no_DMA

	movem.l	(sp)+,d0-a6
	rts

.ModeTable
	dc.l	.Mode0
	dc.l	.Mode1
	dc.l	.Mode2
	dc.l	.Mode3
	dc.l	.Mode4
	dc.l	.IllegalMode
	dc.l	.IllegalMode
	dc.l	.IllegalMode


.IllegalMode
	rts

.Mode0
	rts

.Mode1
	rts

.Mode2
	rts

.Mode3
	rts

.Mode4
	rts

set_HDMAEN	;HDMA enable register

	move.l	d1,d0
	and.l	#$ff,d0
	move.l	d0,SHW_HDMAEnabled(a6)

	rts

set_MEMSEL	;Cycle speed register
	rts

set_TIMEUP	;Video IRQ register
	rts

set_HVBJOY	;Status register
	clr.l	d0
	rts

prg_43hSetJumpTable
	dc.l	set_DMAP0		;4300
	dc.l	set_BBAD0		;4301
	dc.l	set_A1T0L		;4302
	dc.l	set_A1T0H		;4303
	dc.l	set_A1B0		;4304
	dc.l	set_DAS0L		;4305
	dc.l	set_DAS0H		;4306
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL0		;430A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP1		;4310
	dc.l	set_BBAD1		;4311
	dc.l	set_A1T1L		;4312
	dc.l	set_A1T1H		;4313
	dc.l	set_A1B1		;4314
	dc.l	set_DAS1L		;4315
	dc.l	set_DAS1H		;4316
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL1		;431A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP2		;4320
	dc.l	set_BBAD2		;4321
	dc.l	set_A1T2L		;4322
	dc.l	set_A1T2H		;4323
	dc.l	set_A1B2		;4324
	dc.l	set_DAS2L		;4325
	dc.l	set_DAS2H		;4326
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL2		;432A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP3		;4330
	dc.l	set_BBAD3		;4331
	dc.l	set_A1T3L		;4332
	dc.l	set_A1T3H		;4333
	dc.l	set_A1B3		;4334
	dc.l	set_DAS3L		;4335
	dc.l	set_DAS3H		;4336
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL3		;433A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP4		;4340
	dc.l	set_BBAD4		;4341
	dc.l	set_A1T4L		;4342
	dc.l	set_A1T4H		;4343
	dc.l	set_A1B4		;4344
	dc.l	set_DAS4L		;4345
	dc.l	set_DAS4H		;4346
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL4		;434A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP5		;4350
	dc.l	set_BBAD5		;4351
	dc.l	set_A1T5L		;4352
	dc.l	set_A1T5H		;4353
	dc.l	set_A1B5		;4354
	dc.l	set_DAS5L		;4355
	dc.l	set_DAS5H		;4356
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL5		;435A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP6		;4360
	dc.l	set_BBAD6		;4361
	dc.l	set_A1T6L		;4362
	dc.l	set_A1T6H		;4363
	dc.l	set_A1B6		;4364
	dc.l	set_DAS6L		;4365
	dc.l	set_DAS6H		;4366
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL6		;436A
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_DMAP7		;4370
	dc.l	set_BBAD7		;4371
	dc.l	set_A1T7L		;4372
	dc.l	set_A1T7H		;4373
	dc.l	set_A1B7		;4374
	dc.l	set_DAS7L		;4375
	dc.l	set_DAS7H		;4376
	dc.l	HWFail
	dc.l	HWFail
	dc.l	HWFail
	dc.l	set_NTRL7		;437A

set_DMAP0	;DMA Control register

	move.b	d1,SHW_DMA0+DMA_Type(a6)

	rts

set_BBAD0	;DMA Destination register

	move.b	d1,SHW_DMA0+DMA_HWAddr(a6)

	rts

set_A1T0L	;Source address

	move.b	d1,SHW_DMA0+DMA_MemAddrLow(a6)

	rts

set_A1T0H	;Source address

	move.b	d1,SHW_DMA0+DMA_MemAddrHigh(a6)

	rts

set_A1B0	;Source bank address

	move.b	d1,SHW_DMA0+DMA_Bank(a6)

	rts

set_DAS0L	;DMA transfer size & HDMA address register

	move.b	d1,SHW_DMA0+DMA_SizeLow(a6)

	rts

set_DAS0H	;DMA transfer size & HDMA address register

	move.b	d1,SHW_DMA0+DMA_SizeHigh(a6)

	rts

set_NTRL0	;Number of lines for HDMA transfer
	rts

set_DMAP1	;DMA Control register

	move.b	d1,SHW_DMA1+DMA_Type(a6)

	rts

set_BBAD1	;DMA Destination register

	move.b	d1,SHW_DMA1+DMA_HWAddr(a6)

	rts

set_A1T1L	;Source address

	move.b	d1,SHW_DMA1+DMA_MemAddrLow(a6)

	rts

set_A1T1H	;Source address

	move.b	d1,SHW_DMA1+DMA_MemAddrHigh(a6)

	rts

set_A1B1	;Source bank address

	move.b	d1,SHW_DMA1+DMA_Bank(a6)

	rts

set_DAS1L	;DMA transfer size & HDMA address register

	move.b	d1,SHW_DMA1+DMA_SizeLow(a6)

	rts

set_DAS1H	;DMA transfer size & HDMA address register

	move.b	d1,SHW_DMA1+DMA_SizeHigh(a6)

	rts

set_NTRL1	;Number of lines for HDMA transfer
	rts

set_DMAP2	;DMA Control register
	rts

set_BBAD2	;DMA Destination register
	rts

set_A1T2L	;Source address
	rts

set_A1T2H	;Source address
	rts

set_A1B2	;Source bank address
	rts

set_DAS2L	;DMA transfer size & HDMA address register
	rts

set_DAS2H	;DMA transfer size & HDMA address register
	rts

set_NTRL2	;Number of lines for HDMA transfer
	rts

set_DMAP3	;DMA Control register
	rts

set_BBAD3	;DMA Destination register
	rts

set_A1T3L	;Source address
	rts

set_A1T3H	;Source address
	rts

set_A1B3	;Source bank address
	rts

set_DAS3L	;DMA transfer size & HDMA address register
	rts

set_DAS3H	;DMA transfer size & HDMA address register
	rts

set_NTRL3	;Number of lines for HDMA transfer
	rts

set_DMAP4	;DMA Control register
	rts

set_BBAD4	;DMA Destination register
	rts

set_A1T4L	;Source address
	rts

set_A1T4H	;Source address
	rts

set_A1B4	;Source bank address
	rts

set_DAS4L	;DMA transfer size & HDMA address register
	rts

set_DAS4H	;DMA transfer size & HDMA address register
	rts

set_NTRL4	;Number of lines for HDMA transfer
	rts

set_DMAP5	;DMA Control register
	rts

set_BBAD5	;DMA Destination register
	rts

set_A1T5L	;Source address
	rts

set_A1T5H	;Source address
	rts

set_A1B5	;Source bank address
	rts

set_DAS5L	;DMA transfer size & HDMA address register
	rts

set_DAS5H	;DMA transfer size & HDMA address register
	rts

set_NTRL5	;Number of lines for HDMA transfer
	rts

set_DMAP6	;DMA Control register
	rts

set_BBAD6	;DMA Destination register
	rts

set_A1T6L	;Source address
	rts

set_A1T6H	;Source address
	rts

set_A1B6	;Source bank address
	rts

set_DAS6L	;DMA transfer size & HDMA address register
	rts

set_DAS6H	;DMA transfer size & HDMA address register
	rts

set_NTRL6	;Number of lines for HDMA transfer
	rts

set_DMAP7	;DMA Control register
	rts

set_BBAD7	;DMA Destination register
	rts

set_A1T7L	;Source address
	rts

set_A1T7H	;Source address
	rts

set_A1B7	;Source bank address
	rts

set_DAS7L	;DMA transfer size & HDMA address register
	rts

set_DAS7H	;DMA transfer size & HDMA address register
	rts

set_NTRL7	;Number of lines for HDMA transfer
	rts