\initializearticle
\title *The Two Meg Agnus Project*

\author  *Neil Coito*
\netaddress[\network{InterNet}] *ttmaphelp@struad.cts.com*

\author  *Michael Cianflone*
\netaddress[\network{InterNet}] *ttmaphelp@struad.cts.com*

\article

\head *General Information*

  The Two Meg Agnus Project allows the user of an \amc, {\it 2000}, or
{\it 2500} to use the 2 meg Agnus chip and add an additional 1 megabyte of
chip memory to their computer for a total of 2 megabytes of chip RAM.
The Two Meg Agnus Project ({\bf TTMAP}) simply plugs into the Agnus socket
on the motherboard.

  You can build this project by obtaining all the parts yourself and
wire-wrapping it together on a perfboard following the schematics, or
you can order a printed circuit board and solder the parts on
yourself. It is not recommended that you build this on a perfboard
(although it can be done) because doing so may cause the board to fail
do to noise problems, cross talk, and large amounts of capacitance on
the long wires. You can also order The Two Meg Agnus Project in kit
form (or you can order a completely assembled board). The kit includes
most of the parts needed and includes a printed circuit board. See the
section titled {\bf The Two Meg Agnus Project parts list} for a detailed
breakdown of the parts needed and the parts that come with the kit.


\head *The Two Meg Agnus Project parts list*


\hbox to\hsize{\hfil\bf Components:\hfil}

\medskip

\list

\item |RP1-RP3| 47 Ohm $\times$ 5 isolated Resistor pack (10 pin SIP).

\item |C1-C9| 0.01 $\mu$F ceramic capacitor.

\item |U1-U8| 256 $\times$ 4 page mode |DRAM| chips 80ns or faster (20 pin DIP).

\item |U9| PAL20L8 15ns or faster programmed with the
|TTMAP50D_PAL.PLD| file (24 pin |DIP|).

 \item |U10| 2 Mb Agnus |8372B| part \# 318069-03 (84 pin PLCC).
Some |8375B| Agnus chips work also. If the part number on
the chip is |318069-03| then it will work. Both the |8372B|
Agnus and the proper |8375B| Agnus have this part number.
If the Agnus does not say part number |318069-03| on the
chip then it will not work. It must say |318069-03|.

\item |P1| 84 pin |PLCC| Plug with 50 mil.
(All of our kits come with this |$| 20 part already soldered
to the board, even those kits sold ``without parts''.)

\item |W1| Clip lead assembly.

\endlist

\bigskip

\hbox to\hsize{\hfil\bf Miscellaneous Parts:\hfil}

\medskip

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\strut\quad Quantity\quad&\quad Description\quad\cr
\vphantom{\vrule height 4pt}&\cr
\strut\quad 1\quad&\quad TTMAP printed circuit board\quad\cr
\strut\quad 1\quad&\quad 84 pin PLCC socket\quad\cr
\strut\quad 1\quad&\quad Insulation sheet\quad\cr
\strut\quad 1\quad&\quad PLCC chip extractor\quad\cr
\strut\quad 1\quad&\quad 68000 socket extender\quad\cr
\vphantom{\vrule height 4pt}&\cr
\noalign{\hrule}}
}

\head *Theory of operation*

  The Two Meg Agnus Project (TTMAP) is a circuit designed so that the
owner of an \amc, {\sl 2000}, or {\sl 2500} can add the 2 Mb Agnus, along
with another megabyte of RAM, to his/her machine. The Two Meg Agnus
Project contains, within its design, all the circuitry needed to mesh
the motherboard's 1 Mb of chip memory with the 1 Mb of memory on The
Two Meg Agnus Project. This interface will produce 2 Mb of
contiguous chip memory.

  At the heart of The Two Meg Agnus Project's memory controlling
circuitry is a |PAL| (\discretionary{|P|rogramma-}{ble}{|P|rogrammable} |A|rray |L|ogic). A |PAL| is a device that
basically allows us to stuff many different types of logic gates into
one chip. This in turn makes the final project smaller and less
complicated to assemble than when using standard logic chips. The type
of |PAL| we used in this project is a |PAL20L8|. In the file labeled
|TTMAP50D_PAL.PLD| are the equations we use in this |PAL|. These equations
are boolean equations that represent the operation of this device. As
stated in its name, this device is a programmable device that we
programmed to our specifications. The file |TTMAP50D_LOGIC.IFF| is a
graphical representation using logic symbols of what the |PAL| is
simulating. {\it Do not} try to duplicate this design using {\it standard} logic
devices. This is because the large propagation delay caused by all the
|IC|s needed would more than likely cause the design to fail. By using a
|PAL| with a small propagation delay we eliminate this problem. Use the
diagram just for reference only.


  The first and probably the most difficult problem in the circuit
design was to mesh the memory on both the motherboard and The Two Meg
Agnus Project so that the 2 Mb Agnus sees one contiguous chunk of 2
megabytes. The restrictions were: we had to use the lines coming from
the motherboard's Agnus socket, and trace-cutting beyond the norm was
forbidden. We decided to approach the memory as a matrix.

  The complete 2 megabytes of memory is divided into 4 chunks of 512K.
The 1 megabyte of memory on the motherboard is divided into two banks of
512K. The first 512K is controlled by |*RAS0| and the second 512K is
controlled by |*RAS1|. Both banks on the motherboard are controlled by
common |*CASU| and |*CASL| lines. On the computer's motherboard the |*RAS|,
|*CASU|, and |*CASL| lines were directly controlled by the 1 meg Agnus
chip. This same type of configuration was duplicated on the TTMAP
board: 2 chunks of 512K. At this point we renamed the |*CASU| and |*CASL|
on both 1 megabyte chunks of memory. The |*CASU| and |*CASL| signals on the
motherboard are now |*CASU0| and |*CASL0| and the |*CASU| and |*CASL| signals
on the TTMAP board are |*CASU1| and |*CASL1|. On both boards |*RAS0| and
|*RAS1| stay the same. At this point we have four chunks of memory each
with a size of 512K and each chunk controlled by different lines. The
first 512K is controlled by |*RAS0|, |*CASU0|, and |*CASL0|. The second 512K
is controlled by |*RAS1|, |*CASU0|, and |*CASL0|. The third 512K is
controlled by |*RAS0|, |*CASU1|, and |*CASL1|. The fourth 512K is controlled
by |*RAS1|, |*CASU1|, and |*CASL1|.

\bigskip

\hbox to\hsize{\hfil\bf Memory Matrix:\hfil}

\medskip

\hbox to \colwd{\hfil\hbox{%
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{\size{8}{10pt}\selectfont
\put {\lines{Motherboard\cr Bank 2\cr 512 Kb}} at 3 3
\put {\lines{Motherboard\cr Bank 1\cr 512 Kb}} at 3 5
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\put {\lines{TTMAP\cr Bank 1\cr 512 Kb}} at 5 5
}
\put {\tt RAS1} at 1 3
\put {\tt RAS0} at 1 5
\put {\tt\lines{*CASU0\cr *CASL0}} at 3 6.5
\put {\tt\lines{*CASU1\cr *CASL1}} at 5 6.5
\endpicture
}\hfil}

\bigskip

  As you can see in the schematic, the 2 Mb Agnus chip only has |*RAS|,
|*CASU|, and |*CASL| signals coming from it. The job of the |PAL| mentioned
earlier above is to produce the |*RAS0|, |*RAS1|, |*CASU0|, |*CASL0|, |*CASU1|
and |*CASL1| signals needed to access each of the four memory chunks. It does
this basically by |AND|ing the signals with |MA9| at certain times in the memory
cycle. See the |PAL| equations to get an exact idea of what is happening in
the |PAL|.

  In order for a memory location in a Dynamic RAM device to be
addressed, the device must first receive the first half of its address
then a |*RAS| (|R|ow |A|ddress |S|trobe) signal, then it must receive the
second half of its address and a |*CAS| (|C|olumn |A|ddress |S|trobe) signal.
If these signals are received and the timing is correct, an address
has been properly accessed. If the device should receive one signal
and not the other then the device will not be selected and no data
will be read or written. This type of addressing system is called
multiplexed addressing.

  The first thing that happens on a memory cycle in Agnus, is that the
address lines |A9-A17| and |A19| are place on the 2 Mb Agnus' multiplexed
address lines |MA0-MA9|. A short time after that the |*RAS| line from
Agnus goes {\bf low}. The |*RAS0| or |*RAS1| line from the |PAL| then goes {\bf low}
(depending on the value of |MA9| at that point) and latches the |Row|
address into the selected RAM chips. After the |Row| address is latched
into the selected RAM chips, the address lines |A1-A8|, |A18|, and |A20| are
then placed on  Agnus' multiplexed address lines |MA0-MA9|. The {\bf Column}
address lines are then latched into the RAM chips by the |*CAS#0| or
|*CAS#1| lines (depending on the value of |MA9| at that point) from the
|PAL| going {{\bf low}}. Once the RAM chips have received their {\bf Row}
address and {\bf Column} address they are now ready to be accessed. The operation to
be performed on the RAM chips is determined by the control lines such as |*WE|
(Write Enable) and |*OE| (Output Enable) which are set during the memory cycle.
If |*WE| is {\bf low} then a write operation is being performed on the RAM
chips. If |*OE| is {\bf low} then a read operation in being performed on the RAM
chips. Note that not all dynamic RAM chips have the |*OE| line, on these chips
when |*WE| is {\it high} it is assumed that a read operation is taking place.

  The operation of this board is very simple in its decoding of the
multiplexed address lines. The |PAL| uses address line |MA9| to determine
which |*RAS#| and |*CAS#| lines to activate, which in turn selects
different chunks of memory. See the |PAL| equations, and by following
the logic and the comments you should be able see how the |PAL| decodes
the address lines and determines which part of memory is being
accessed.

{\signaturewidth=15pc
\makesignature}

\endarticle