;   divu
		;
		;   (c)Copyright 1990, Matthew Dillon, All Rights Reserved
		;
		;   32/32->32 divide
		;
		;   args on stack, return result on stack
		;
		;   CANNOT DESTROY ANY REGS
		;
		;	8sp	10sp	    s1	    numer   s1/s2
		;	4sp	6sp	    s2	    denom
		;
		;   NOTE, due to macro and movem off(An),... we cannot use
		;   DAS.

		section text,code
	;   IFD MODULO
	;	xdef	__modu
	;	xdef	__mods
	;   ENDC
	;   IFND MODULO
		xdef	__divu
		xdef	__divs
	;   ENDC

	;   IFD MODULO
__modu: ;
	;   ENDC
	;   IFND MODULO
__divu:
	;   ENDC
modivu
		tst.w	0+4(sp)         ;   32 bit denom
		bne	n10
		move.l	D0,-(sp)        ;   16 bit denom, ? bit num
		move.l	4+8(sp),D0
		divu.w	4+6(sp),D0
		bvs	n20		;   result > 16 bits (denom <= 16 bits)
	;   IFD MODULO
	;	swap	D0
	;   ENDC
		move.w	#0,4+8(sp)
		move.w	D0,4+10(sp)
		move.l	(sp)+,D0
		move.l	(sp)+,(sp)
		rts

		;   32 bit denom

n10
		tst.w	0+8(sp)         ;   numerator > 16 bits?
		bne	n11
	;   IFD MODULO
	;	;move.l 0+8(sp),0+8(sp) ;   10 % 999 == 10
	;   ENDC
	;   IFND MODULO
		move.l	#0,0+8(sp)      ;   no, num < den, result 0
	;   ENDC
		move.l	(sp)+,(sp)
		rts

		;   32 bit num / 32 bit denom (both nums > 16 bits).  Thus,
		;   16 bit result.
		;
		;   D0 into D1|D2,  D3 result,	iterate 16 times
		;
		;   remainder is in D1 at end

n11:		movem.l D0-D3,-(sp)
		move.w	#2,-(sp)        ;   iteration counter
		moveq.l #0,D3		;   result
		moveq.l #0,D1
		move.l	18+4(sp),D0
		movem.w 18+8(sp),D1/D2  ;   D1 has first 16 bits of numerator
		swap	D2

ITER32		MACRO
		asl.l	#1,D3		; 8
		asl.l	#1,D2		; 8
		roxl.l	#1,D1		; 8
		cmp.l	D0,D1		; 6  D1 - D0, carry if D1 < D0
		bcs.s	N11\@		; 10
		sub.l	D0,D1		; 8  D1 = D1 - D0
		addq.l	#1,D3		; 8
N11\@:
		ENDM

IterLoop

		ITER32
		ITER32
		ITER32
		ITER32
		ITER32
		ITER32
		ITER32
		ITER32

		subq.w	#1,(sp)
		bne	IterLoop

		lea	2(sp),sp
	;   IFD MODULO
	;	move.l	D1,16+8(sp)
	;   ENDC
	;   IFND MODULO
		move.l	D3,16+8(sp)
	;   ENDC
		movem.l (sp)+,D0-D3
		move.l	(sp)+,(sp)
		rts

		;
		;   result > 16 bits, thus  num > 16 bits & denom <= 16 bits
		;
		;   iterate 32 times

n20		move.l	(sp)+,D0
		movem.l D0-D3,-(sp)
		move.w	#4,-(sp)
		moveq.l #0,D3
		moveq.l #0,D1
		move.l	18+4(sp),D0
		move.l	18+8(sp),D2
		bra	IterLoop

		;   signed divide

	;   IFD MODULO
__mods: ;
	;   ENDC
	;   IFND MODULO
__divs:
	;   ENDC
		tst.l	0+4(sp)
		bmi.s	s50
		tst.l	0+8(sp)
		bpl	modivu
		neg.l	0+8(sp)
		bra.s	s76

s50		tst.l	0+8(sp)
		bpl.s	s75
		neg.l	0+4(sp)
		neg.l	0+8(sp)
		bra	modivu

s75		neg.l	0+4(sp)
s76		move.l	0+8(sp),-(sp)
		move.l	4+4(sp),-(sp)
		bsr	modivu
		neg.l	(sp)
		move.l	(sp)+,0+8(sp)
		move.l	(sp)+,(sp)
		rts

		END