@DATABASE @NODE MAIN 16C7184 * 16C7184 HyperSource© include file for 16C71/16C84 * © 1998 RST Ralf Steines Trier, ALL RIGHTS RESERVED * * source: Microchip databook 1994 * @{" 16C71/84 CPU-CORE " link "16C7184_CPU-CORE"} @{" 16C71/84 INTERRUPTS " link "16C7184_INTERRUPTS"} @{" 16C71/84 IO-PORTS " link "16C7184_IO-PORTS"} @{" 16C71 ADCs " link "16C71_ADCs"} @{" 16C71/84 TIMERS " link "16C7184_TIMERS"} @{" 16C84 PROM " link "16C84_PROM"} * Values with a '*' in front of them show the defaults after a RESET. @ENDNODE @NODE 16C7184_INTERRUPTS **************************** * INTERRUPT VECTORS * **************************** ; THESE ARE NO VECTORS BUT PROGRAM MEMORY LOCATIONS THE CPU JUMPS TO ; MUST CONTAIN OBJECT CODE TO JUMP TO YOUR RELATING ROUTINES ! C_RESET = $0000 ; C_IRQ = $0004 ; ******************************* * INTERRUPT CONTROL REGISTERS * ******************************* INTCON = REGS+$0B ; INTERRUPT CONTROL REGISTER GIE = 7 ; GLOBAL INTERRUPT ENABLE ; *0= DISABLE ; 1= ENABLE .IFD HAS_ADC ; 16C71 ONLY ADIE = 6 ; A/D INTERRUPT ENABLE BIT ; *0= DISABLE ADIF INTERRRUPT ; 1= ENABLE ADIF INTERRRUPT .ENDIF .IFD HAS_PROM ; 16C84 ONLY EEIE = 6 ; EEPROM WRITE INTERRUPT ENABLE BIT ; *0= DISABLE EEIF INTERRRUPT ; 1= ENABLE EEIF INTERRRUPT .ENDIF T0IE = 5 ; TMR0 INTERRUPT ENABLE BIT ; *0= DISABLE T0IF INTERRRUPT ; 1= ENABLE T0IF INTERRRUPT INTE = 4 ; INT INTERRUPT ENABLE BIT ; *0= DISABLE INTF INTERRRUPT ; 1= ENABLE INTF INTERRRUPT RBIE = 3 ; RBIF INTERRUPT ENABLE BIT ; *0= DISABLE RBIF INTERRRUPT ; 1= ENABLE RBIF INTERRRUPT T0IF = 2 ; TIMER 0 OVERFLOW INTERRUPT FLAG ; 1= TMR0 OVERFLOWS ; *0= RESET IN SOFTWARE ! INTF = 1 ; INT INTERRUPT FLAG ; 1= INT INTERRUPT OCCURES ; *0= RESET IN SOFTWARE ! RBIF = 0 ; RB PORT CHANGE INTERRUPT ; 1= PORT B[7:5] CHANGED ; 0= RESET IN SOFTWARE ! ; (*UNDEFINED AFTER RESET) @ENDNODE @NODE 16C7184_CPU-CORE ************************ * CPU CORE * ************************ IND = REGS+$00 ; USE CONTENTS OF FSR TO ADDRESS DATA MEMORY ; (NO PHYSICAL REGISTER) PCL = REGS+$02 ; LOW ORDER 8 BITS OF PC ; (*0 AFTER RESET) FSR = REGS+$04 ; INDIRECT DATA MEMORY ADDRESS POINTER 0 ; LOW ORDER 8 BITS, 9TH BIT = IRP IN STATUS ; (*UNDEFINED AFTER RESET) PCLATH = REGS+$0A ; HOLDING REGISTER FOR HIGH BYTE OF PC ; (*0 AFTER RESET) STATUS = REGS+$03 ; STATUS REGISTER IRP = 7 ; REGISTER PAGE SELECT BIT ; FOR INDIRECT ADDRESSING ; *0= PAGE 0,1 $000 - $0FF ; 1= PAGE 2,3 $100 - $1FF RP1 = 6 ; REGISTER PAGE SELECT BITS RP0 = 5 ; FOR DIRECT ADDRESSING ; RP1 RP0 ; *0 *0 PAGE 0 $000 - $07F ; 0 1 PAGE 1 $080 - $0FF ; 1 0 PAGE 2 $100 - $17F ; 1 1 PAGE 3 $180 - $1FF TO = 4 ; TIMEOUT BIT, ACTIVE LOW ! ; 0= WATCHDOG TIMEOUT OCCURED ; *1= SET BY CLRWDT, SLEEP, POWER UP PD = 3 ; POWER DOWN BIT, ACTIVE LOW ; 0= POWER DOWN OCCURED ; OR SLEEP WAS EXECUTED ; *1= SET BY CLRWDT OR POWER UP Z = 2 ; ZERO BIT ; 1= LAST ARITHMETIC OPERATION RESULTS 0 ; MOVF ALSO AFFECT ZERO BIT ! ; (*UNDEFINED AFTER RESET) DC = 1 ; DIGIT CARRY / -BORROW BIT ; 1= ADDWF,ADDLW OVERFLOWED BIT 3 ; SUBWF,SUBLW UNDERFLOWED BIT 3 ; (*UNDEFINED AFTER RESET) C = 0 ; CARRY / -BORROW BIT ; 1= ADDWF,ADDLW OVERFLOWED BIT 7 ; SUBWF,SUBLW UNDERFLOWED BIT 7 ; RRF AND RLF ALSO AFFECT C ! ; (*UNDEFINED AFTER RESET) @ENDNODE @NODE 16C7184_IO-PORTS **************************** * INPUT/ OUTPUT PORTS * **************************** TRISA = REG1+$05 ; DATA DIRECTION REGISTER FOR PORT A TRISA4 = 4 ; (0=OUT, *1=IN) TRISA3 = 3 ; (0=OUT, *1=IN) TRISA2 = 2 ; (0=OUT, *1=IN) TRISA1 = 1 ; (0=OUT, *1=IN) TRISA0 = 0 ; (0=OUT, *1=IN) PORTA = REG0+$05 ; PORT A DATA REGISTER ; (*UNDEFINED AFTER RESET) RA4 = 4 ; I/O (SCHMITT TRIGGER/OPEN DRAIN) USE PULLUP RA3 = 3 ; I/O OR AIN3 OR VREF RA2 = 2 ; I/O OR AIN2 RA1 = 1 ; I/O OR AIN1 RA0 = 0 ; I/O OR AIN0 T0CKI = 4 ; T0CKI EXTERNAL INTERRUPT INPUT ; ALSO EXTERNAL CLOCK IN FOR TMR0 TRISB = REG1+$06 ; DATA DIRECTION REGISTER FOR PORT B TRISB7 = 7 ; (0=OUT, *1=IN) TRISB6 = 6 ; (0=OUT, *1=IN) TRISB5 = 5 ; (0=OUT, *1=IN) TRISB4 = 4 ; (0=OUT, *1=IN) TRISB3 = 3 ; (0=OUT, *1=IN) TRISB2 = 2 ; (0=OUT, *1=IN) TRISB1 = 1 ; (0=OUT, *1=IN) TRISB0 = 0 ; (0=OUT, *1=IN) PORTB = REG0+$06 ; PORT B DATA REGISTER ; (*UNDEFINED AFTER RESET) RB7 = 7 ; I/O RB6 = 6 ; I/O RB5 = 5 ; I/O RB4 = 4 ; I/O RB3 = 3 ; I/O RB2 = 2 ; I/O RB1 = 1 ; I/O RB0 = 0 ; I/O INT = 0 ; INT EXTERNAL INTERRUPT INPUT (SCHMITT TRIGGER) @ENDNODE @NODE 16C7184_TIMERS **************************** * TIMER REGISTERS * **************************** TMR0 = REG0+$01 ; TIMER 0 COUNTER REGISTER ; (*UNDEFINED AFTER RESET) RTCC = REG0+$01 ; JUST FOR COMPATIBLITY OPTION = REG1+$01 ; OPTION REGISTER (must be column 0 because of opc.) RBPU = 7 ; PORTB PULL-UP ENABLE, ACTIVE LOW ; 0= PULL-UPS ARE ENABLED BY INDIVIDUAL ; PORT-LATCH VALUES ; *1= PULL-UPS ARE DISABLED OVERRIDING ; ANY PORT-LATCH VALUE INTEDG = 6 ; INT INTERRUPT EDGE SELECT ; 0= INTERRUPT ON FALLING EDGE ; *1= INTERRUPT ON RISING EDGE RTS = 5 ; TIMER 0 SIGNAL SOURCE ; 0= INTERNAL INSTRUCTION CYCLE CLOCK ; *1= TRANSITION ON RA4/T0CKI PIN RTE = 4 ; TIMER 0 SIGNAL EDGE ; 0= INCREMENT ON RISING EDGE ON RA4/T0CKI ; *1= INCREMENT ON FALLING EDGE ON RA4/T0CKI PSA = 3 ; PRESCALER ASSIGNMENT ; 0= TMR0 ; *1= WDT PS2 = 2 ; PRESCALER VALUE PS1 = 1 ; PS2 PS1 PS0 TMR0 RATE WDT RATE PS0 = 0 ; 0 0 0 1:2 1:1 ; 0 0 1 1:4 1:2 ; 0 1 0 1:8 1:4 ; 0 1 1 1:16 1:8 ; 1 0 0 1:32 1:16 ; 1 0 1 1:64 1:32 ; 1 1 0 1:128 1:64 ; *1 *1 *1 1:256 1:128 @ENDNODE @NODE 16C71_ADCs ****************************************** * ANALOG -> DIGITAL CONVERSION REGISTERS * ****************************************** .IFD HAS_ADC ; 16C71 ONLY ADRES = REGS+$09 ; A/D RESULT REGISTER ; (*UNDEFINED AFTER RESET) ADCON0 = REG0+$08 ; A/D CONTROL REGISTER 0 ADCS1 = 7 ; A/D CONVERSION CLOCK SELECT ADCS0 = 6 ; ADCS1 ADCS1 CLOCK RATE ; *0 *0 OSC/2 ; 0 1 OSC/8 ; 1 0 OSC/32 ; 1 0 F_RC (RC-OSCILLATOR) ; A/D CHANNEL SELECT CHS1 = 4 ; CS1 CS0 CHANNEL CHS0 = 3 ; *0 *0 RA0/AIN0 ; 0 1 RA1/AIN1 ; 1 0 RA2/AIN2 ; 1 1 RA3/AIN3 GODONE = 2 ; A/D CONVERSION STATUS BIT ; *0= A/D CONVERSION NOT ON PROGRESS ; OR COMPLETED. ; 1= CONVERSION IN PROGRESS ; SET THIS BIT TO START CONVERSION ADIF = 1 ; A/D CONVERTER INTERRUPT FLAG ; *0= NO ADIF INTRRUPT ; 1= ADIF INTERRRUPT CONVERSION COMPLETED ADON = 0 ; A/D ON BIT ; *0= A/D MODULE SHUT OFF, NO POWER DRAIN ; 1= A/D MODULE IS OPERATING ADCON1 = REG1+$08 ; A/D CONTROL REGISTER 1 ; A/D PORT CONFIGURATION BITS PCFG1 = 1 ; PC1 PC0 A0 A1 A2 A3 REF PCFG0 = 0 ; *0 *0 A A A A VDD ; 0 1 A A A REF RA3 ; 1 0 A A D D VDD ; 1 1 D D D D VDD .ENDIF @ENDNODE @NODE 16C84_PROM ************************** * PROGRAMMING REGISTERS * ************************** .IFD HAS_PROM ; 16C84 ONLY EEDATA = REG0+$08 ; EEPROM DATA REGISTER ; (*UNDEFINED AFTER RESET) EEADR = REG0+$09 ; EEPROM ADDRESS REGISTER ; (*UNDEFINED AFTER RESET) EECON1 = REG1+$08 ; EEPROM CONTROL REGISTER 1 EEIF = 4 ; EEPROM WRITE COMPLETION INTERRUPT FLAG ; 1= WRITE IS COMPLETED ; *0= RESET IN SOFTWARE ! ; CORRESPONDING ENALBLE EEIE IN INTCON ! WRERR = 3 ; EEPROM WRITE ERROR ; 1= WRITE OPERANTION IS PREMATURELY ; TERMIN. BY A -MCLR (IN SLEEP OR NORMAL) ; OR A WDT RESET DURING NORMAL OPERATION ; (*UNDEFINED AFTER RESET) WREN = 2 ; EEPROM WRITE ENABLE BIT ; *0= WRITE INHIBITED ; 1= WRITE ALLOWED WR = 1 ; EEPROM WRITE CONTROL BIT ; 1= INITIATE A WRITE CYCLE ; *0= CLEARED BY HARDWARE AFTER WRITE RD = 0 ; EEPROM READ CONTROL BIT ; 1= INITIATE A READ CYCLE ; *0= CLEARED BY HARDWARE AFTER READ EECON2 = REG1+$09 ; EEPROM CONTROL REGISTER 2 ; (NOT A PHYSICAL REGISTER) .ENDIF @ENDNODE