@DATABASE
@NODE MAIN HC05P
* 68HC05Px HyperSource© include file
* © 1998 RST Ralf Steines Trier, ALL RIGHTS RESERVED
*
* source: MUCBBS, HC05 C-headers
*

    @{" HC05P  CPU-CORE      " link "HC05P_CPU-CORE"}
    @{" HC05P  INTERRUPTS    " link "HC05P_INTERRUPTS"}

    @{" HC05P  IO-PORTS      " link "HC05P_IO-PORTS"}

    @{" HC05P  TIMERS        " link "HC05P_TIMERS"}

@ENDNODE
@NODE HC05P_CPU-CORE
************************
*       CPU CORE       *
************************

; SUPPORTS: STOP WAIT MUL


@ENDNODE
@NODE HC05P_INTERRUPTS
****************************
*    INTERRUPT VECTORS     *
****************************

  V_TMR     = IRQS+$08 ;
  V_IRQ     = IRQS+$0A ;
  V_SWI     = IRQS+$0C ;
  V_RES     = IRQS+$0E ;


@ENDNODE
@NODE HC05P_IO-PORTS
****************************
*   INPUT/ OUTPUT PORTS    *
****************************

  PORTA     = REGS+$00 ; PORT A DATA REGISTER

        PA7       = %10000000   ; I/O
        PA6       = %01000000   ; I/O
        PA5       = %00100000   ; I/O
        PA4       = %00010000   ; I/O
        PA3       = %00001000   ; I/O
        PA2       = %00000100   ; I/O
        PA1       = %00000010   ; I/O
        PA0       = %00000001   ; I/O

  PORTB     = REGS+$01 ; PORT B DATA REGISTER

        PB7       = %10000000   ; I/O
        PB6       = %01000000   ; I/O
        PB5       = %00100000   ; I/O

  PORTC     = REGS+$02 ; PORT C DATA REGISTER

        PC7       = %10000000   ; I/O
        PC6       = %01000000   ; I/O
        PC5       = %00100000   ; I/O
        PC4       = %00010000   ; I/O
        PC3       = %00001000   ; I/O
        PC2       = %00000100   ; I/O
        PC1       = %00000010   ; I/O
        PC0       = %00000001   ; I/O

  PORTD     = REGS+$03 ; PORT D DATA REGISTER (BIT6=PD5?)

        PD7       = %10000000   ; IN

        TCAP      = %10000000   ; TIMER INPUT CAPTURE IN

  DDRA      = REGS+$04 ; DATA DIRECTION REGISTER FOR PORT A

        DDA7      = %10000000   ; *0=IN 1=OUT
        DDA6      = %01000000   ; *0=IN 1=OUT
        DDA5      = %00100000   ; *0=IN 1=OUT
        DDA4      = %00010000   ; *0=IN 1=OUT
        DDA3      = %00001000   ; *0=IN 1=OUT
        DDA2      = %00000100   ; *0=IN 1=OUT
        DDA1      = %00000010   ; *0=IN 1=OUT
        DDA0      = %00000001   ; *0=IN 1=OUT

  DDRB      = REGS+$05 ; DATA DIRECTION REGISTER FOR PORT B

        DDB7      = %10000000   ; *0=IN 1=OUT
        DDB6      = %01000000   ; *0=IN 1=OUT
        DDB5      = %00100000   ; *0=IN 1=OUT

  DDRC      = REGS+$06 ; DATA DIRECTION REGISTER FOR PORT C

        DDC7      = %10000000   ; *0=IN 1=OUT
        DDC6      = %01000000   ; *0=IN 1=OUT
        DDC5      = %00100000   ; *0=IN 1=OUT
        DDC4      = %00010000   ; *0=IN 1=OUT
        DDC3      = %00001000   ; *0=IN 1=OUT
        DDC2      = %00000100   ; *0=IN 1=OUT
        DDC1      = %00000010   ; *0=IN 1=OUT
        DDC0      = %00000001   ; *0=IN 1=OUT


@ENDNODE
@NODE HC05P_TIMERS
****************************
*     TIMER REGISTERS      *
****************************

  TCR       = REGS+$12 ; TIMER CONTROL REGISTER

        ICIE      = %10000000   ; INPUT CAPTURE INTERRUPT ENABLE
                                ; *0= DISABLED
                                ;  1= ENABLED

        OCIE      = %01000000   ; OUTPUT COMPARE INTERRUPT ENABLE
                                ; *0= DISABLED
                                ;  1= ENABLED

        TOIE      = %00100000   ; TIMER OVERFLOW INTERRUPT ENABLE
                                ; *0= DISABLED
                                ;  1= ENABLED

        IEGE      = %00000010   ; INPUT EDGE SELECT

        OLVL      = %00000001   ; OUTPUT LEVEL SELECT

  TSR       = REGS+$13 ; TIMER STATUS REGISTER
                       ; *0= NO EVENT
                       ;  1= EVENT OCCURED

        ICF       = %10000000   ; INPUT CAPTURE FLAG

        OCF       = %01000000   ; OUTPUT COMPARE FLAG

        TOF       = %00100000   ; TIMER OVERFLOW FLAG

  ICHR      = REGS+$14   ; INPUT CAPTURE REG HIGH BYTE
  ICLR      = REGS+$15   ; INPUT CAPTURE REG LOW BYTE

  OCHR      = REGS+$16   ; OUTPUT COMPARE REG HIGH BYTE
  OCLR      = REGS+$17   ; OUTPUT COMPARE REG LOW BYTE

  TCHR      = REGS+$18   ; TIMER COUNTER REGISTER HIGH BYTE
  TCLR      = REGS+$19   ; TIMER COUNTER REGISTER LOW BYTE

  ACHR      = REGS+$1A   ; ALTERNATE COUNT REG HIGH BYTE
  ACLR      = REGS+$1B   ; ALTERNATE COUNT REG LOW BYTE


@ENDNODE