@DATABASE @NODE MAIN HC05C * 68HCx05Cx HyperSource© include file * © 1998 RST Ralf Steines Trier, ALL RIGHTS RESERVED * * source: MUCBBS, HC05 C-headers * @{" HC05C CPU-CORE " link "HC05C_CPU-CORE"} @{" HC05C INTERRUPTS " link "HC05C_INTERRUPTS"} @{" HC05C IO-PORTS " link "HC05C_IO-PORTS"} @{" HC05C SPI-INTERFACE " link "HC05C_SPI-INTERFACE"} @{" HC05C SCI-INTERFACE " link "HC05C_SCI-INTERFACE"} @{" HC05C TIMERS " link "HC05C_TIMERS"} @{" HC705C PROM " link "HC705C_PROM"} @{" HC805C PROM " link "HC805C_PROM"} @ENDNODE @NODE HC05C_CPU-CORE ************************ * CPU CORE * ************************ ; SUPPORTS: STOP WAIT MUL @ENDNODE @NODE HC05C_INTERRUPTS **************************** * INTERRUPT VECTORS * **************************** V_SPI = IRQS+$04 ; V_SCI = IRQS+$06 ; V_TMR = IRQS+$08 ; V_IRQ = IRQS+$0A ; V_SWI = IRQS+$0C ; V_RES = IRQS+$0E ; @ENDNODE @NODE HC05C_IO-PORTS **************************** * INPUT/ OUTPUT PORTS * **************************** PORTA = REGS+$00 ; PORT A DATA REGISTER PA7 = %10000000 ; I/O PA6 = %01000000 ; I/O PA5 = %00100000 ; I/O PA4 = %00010000 ; I/O PA3 = %00001000 ; I/O PA2 = %00000100 ; I/O PA1 = %00000010 ; I/O PA0 = %00000001 ; I/O PORTB = REGS+$01 ; PORT B DATA REGISTER PB7 = %10000000 ; I/O PB6 = %01000000 ; I/O PB5 = %00100000 ; I/O PB4 = %00010000 ; I/O PB3 = %00001000 ; I/O PB2 = %00000100 ; I/O PB1 = %00000010 ; I/O PB0 = %00000001 ; I/O PORTC = REGS+$02 ; PORT C DATA REGISTER PC7 = %10000000 ; I/O PC6 = %01000000 ; I/O PC5 = %00100000 ; I/O PC4 = %00010000 ; I/O PC3 = %00001000 ; I/O PC2 = %00000100 ; I/O PC1 = %00000010 ; I/O PC0 = %00000001 ; I/O PORTD = REGS+$03 ; PORT D DATA REGISTER PD7 = %10000000 ; IN PD5 = %00100000 ; PD4 = %00010000 ; PD3 = %00001000 ; PD2 = %00000100 ; PD1 = %00000010 ; PD0 = %00000001 ; SS = %00100000 ; SPI SLAVE SELECT INPUT (ACTIVE LOW) SCK = %00010000 ; SPI CLOCK I/O MOSI = %00001000 ; SPI MASTER OUT / SLAVE IN MISO = %00000100 ; SPI MASTER IN / SLAVE OUT TXD = %00000010 ; SCI TRANSMIT DATA OUTPUT RXD = %00000001 ; SCI RECEIVE DATA INPUT DDRA = REGS+$04 ; DATA DIRECTION REGISTER FOR PORT A DDA7 = %10000000 ; *0=IN 1=OUT DDA6 = %01000000 ; *0=IN 1=OUT DDA5 = %00100000 ; *0=IN 1=OUT DDA4 = %00010000 ; *0=IN 1=OUT DDA3 = %00001000 ; *0=IN 1=OUT DDA2 = %00000100 ; *0=IN 1=OUT DDA1 = %00000010 ; *0=IN 1=OUT DDA0 = %00000001 ; *0=IN 1=OUT DDRB = REGS+$05 ; DATA DIRECTION REGISTER FOR PORT B DDB7 = %10000000 ; *0=IN 1=OUT DDB6 = %01000000 ; *0=IN 1=OUT DDB5 = %00100000 ; *0=IN 1=OUT DDB4 = %00010000 ; *0=IN 1=OUT DDB3 = %00001000 ; *0=IN 1=OUT DDB2 = %00000100 ; *0=IN 1=OUT DDB1 = %00000010 ; *0=IN 1=OUT DDB0 = %00000001 ; *0=IN 1=OUT DDRC = REGS+$06 ; DATA DIRECTION REGISTER FOR PORT C DDC7 = %10000000 ; *0=IN 1=OUT DDC6 = %01000000 ; *0=IN 1=OUT DDC5 = %00100000 ; *0=IN 1=OUT DDC4 = %00010000 ; *0=IN 1=OUT DDC3 = %00001000 ; *0=IN 1=OUT DDC2 = %00000100 ; *0=IN 1=OUT DDC1 = %00000010 ; *0=IN 1=OUT DDC0 = %00000001 ; *0=IN 1=OUT @ENDNODE @NODE HC05C_SPI-INTERFACE ***************************************** * SERIAL PERIPHERAL INTERFACE REGISTERS * ***************************************** SPCR = REGS+$0A ; SPI CONTROL REGISTER SPIE = %10000000 ; SPI INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED SPE = %01000000 ; SPI SYSTEM ENABLE ; *0= DISABLED ; 1= ENABLED MSTR = %00010000 ; MASTER/SLAVE MODE SELECT ; *0=SLAVE MODE ; 1=MASTER MODE CPOL = %00001000 ; CLOCK POLARITY ; *0= CLOCK RETURNS TO LOW ; 1= CLOCK RETURNS TO HIGH CPHA = %00000100 ; CLOCK PHASE ; *0= TRIGGER ON FIRST CLOCK CHANGE ; (FROM CPOL TO OPPOSITE LEVEL) ; 1= TRIGGER ON SECOND CLOCK CHANGE ; (FROM OPPOSITE TO CPOL LEVEL) SPR1 = %00000010 ; SPI CLOCK (SCK) RATE BIT SPR0 = %00000001 ; SPR1 SPR0 E DIV BY ; *0 *0 2 ; 0 1 4 ; 1 0 16 ; 1 1 32 SPSR = REGS+$0B ; SPI STATUS REGISTER ; *0= NO EVENT HAPPENED ; 1= EVENT OCCURED SPIF = %10000000 ; SPI INTERRUPT REQUEST FLAG WCOLF = %01000000 ; WRITE COLLISION STATUS FLAG MODF = %00010000 ; SPI MODE ERROR INTERRUPT STATUS FLAG SPDR = REGS+$0C ; SPI DATA REGISTER @ENDNODE @NODE HC05C_SCI-INTERFACE ********************************************* * SERIAL COMMUNICATIONS INTERFACE REGISTERS * ********************************************* BAUD = REGS+$0D ; SCI BAUD RATE CONTROL REGISTER ;? TCLR = %10000000 ; CLEAR BAUD COUNTER CHAIN (TEST ONLY) ; *0 = NORMAL OPERATION ; 1 = CLEAR COUNTERS SCP1 = %00100000 ; SERIAL PRESCALER SELECTS SCP0 = %00010000 ; SCP1 SCP0 DIV E BY ; *0 *0 1 ; 0 1 3 ; 1 0 4 ; 1 1 13 ;? RCKB = %00001000 ; SCI BAUD RATE CLOCK TEST (TEST ONLY) ; *0 = NORMAL OPERATION ; 1 = TEST MODE SCR2 = %00000100 ; SCI RATE SELECT BIT 2 THRU BIT 0 SCR1 = %00000010 ; SCR2 SCR1 SCR0 PRESC OUT DIV BY SCR0 = %00000001 ; 0 0 0 1 ; 0 0 1 2 ; 0 1 0 4 ; 0 1 1 8 ; 1 0 0 16 ; 1 0 1 32 ; 1 1 0 64 ; 1 1 1 128 ; *? ? ? UNDEFINED AFTER RESET! SCCR1 = REGS+$0E ; SCI CONTROL REGISTER 1 R8 = %10000000 ; RECEIVE BIT 8 ; (*UNDEFINED AFTER RESET) T8 = %01000000 ; TRANSMIT BIT 8 ; (*UNDEFINED AFTER RESET) M = %00010000 ; MODE SELECT ; *0= 1 START, 8 DATA, 1 STOP ; 1= 1 START, 8 DATA, 9TH DATA, 1 STOP BIT WAKE = %00001000 ; WAKE = WAKE UP (BY ADDRESS MARK/IDLE) ; *0= WAKE UP BY IDEL LINE ; 1= WAKE UP BY ADDRESS MARK SCCR2 = REGS+$0F ; SCI CONTROL REGISTER 2 TIE = %10000000 ; TRANSMIT INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED TCIE = %01000000 ; TRANSMIT COMPLETE INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED RIE = %00100000 ; RECEIVER INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED ILIE = %00010000 ; IDLE LINE INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED TE = %00001000 ; TRANSMITER ENABLE (TOGGLE TO QUEUE IDLE CHAR) ; *0= OFF ; 1= ON RE = %00000100 ; RECEIVER ENABLE ; *0= OFF ; 1= ON RWU = %00000010 ; RECEIVER WAKE-UP CONTROL ; *0= NORMAL ; 1= RECEIVER ASLEEP SBK = %00000001 ; SEND BREAK ; *0= DISABLED ; 1= SEND BREAK SCSR = REGS+$10 ; SCI STATUS REGISTER ; *0= NO EVENT HAPPENED ; 1= EVENT OCCURED TDRE = %10000000 ; TRANSMIT DATA REG EMPTY FLAG TC = %01000000 ; TRANSMIT COMPLETE FLAG RDRF = %00100000 ; RECEIVE DATA REG FULL FLAG IDLE = %00010000 ; IDLE LINE DETECTED FLAG OR = %00001000 ; OVER-RUN ERROR FLAG NF = %00000100 ; NOISE ERROR FLAG FE = %00000010 ; FRAMING ERROR FLAG SCDAT = REGS+$11 ; SCI DATA REGISTER ; RECEIVE AND TRANSMIT DOUBLE BUFFERED @ENDNODE @NODE HC05C_TIMERS **************************** * TIMER REGISTERS * **************************** TCR = REGS+$12 ; TIMER CONTROL REGISTER ICIE = %10000000 ; INPUT CAPTURE INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED OCIE = %01000000 ; OUTPUT COMPARE INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED TOIE = %00100000 ; TIMER OVERFLOW INTERRUPT ENABLE ; *0= DISABLED ; 1= ENABLED IEGE = %00000010 ; INPUT EDGE SELECT OLVL = %00000001 ; OUTPUT LEVEL SELECT TSR = REGS+$13 ; TIMER STATUS REGISTER ; *0= NO EVENT ; 1= EVENT OCCURED ICF = %10000000 ; INPUT CAPTURE FLAG OCF = %01000000 ; OUTPUT COMPARE FLAG TOF = %00100000 ; TIMER OVERFLOW FLAG ICHR = REGS+$14 ; INPUT CAPTURE REG HIGH BYTE ICLR = REGS+$15 ; INPUT CAPTURE REG LOW BYTE OCHR = REGS+$16 ; OUTPUT COMPARE REG HIGH BYTE OCLR = REGS+$17 ; OUTPUT COMPARE REG LOW BYTE TCHR = REGS+$18 ; TIMER COUNTER REGISTER HIGH BYTE TCLR = REGS+$19 ; TIMER COUNTER REGISTER LOW BYTE ACHR = REGS+$1A ; ALTERNATE COUNT REG HIGH BYTE ACLR = REGS+$1B ; ALTERNATE COUNT REG LOW BYTE ************************************** * COMPUTER OPERATING PROPERLY (COP) * ************************************** .IFD HAS_COP ; HC705C8 ONLY COPCR = REGS+$1E ; COP CONTROL REGISTER COPF = %00010000 ; COP TIMEOUT FLAG ; *0= OK ; 1= COP TIMEOUT OCCURED CME = %00001000 ; CLOCK MONITOR ENABLE ; *0= DISABLED ; 1= SLOW OR STOPPED CLOCKS CAUSE RESET COPE = %00000100 ; COP ENABLE ; *0= DISABLED ; 1= COP TIMEOUT CAUSES RESET CM1 = %00000010 ; COP TIMER RATE SELECT BITS CM0 = %00000001 ; CM1 CM0 E/2^15 DIV BY ; *0 *0 1 ; 0 1 4 ; 1 0 16 ; 1 1 64 .ENDIF @ENDNODE @NODE HC705C_PROM **************************** * PROGRAMMING REGISTERS * **************************** .IFD HAS_PROM7 ; HC705C8 ONLY PR = REGS+$1C ; PROGRAMMING REGISTER LAT = %00000100 ; LATCH ENABLE PGM = %00000001 ; PROGRAM ENABLE ; *0= PROGRAM POWER SWITCHED OFF ; 1= PROGRAM POWER SWITCHED ON MOR = IRQS-1 ; MASK OPTION REGISTER ($1FDF) RAM0 = %10000000 ; DATA ROM WINDOW ENABLE ; 0= RAM $30-$100 ; 1= RAM $50-$100 ROM $20-$50 RAM1 = %00100000 ; PROGRAM RAM WINDOW ENABLE (BITS 5+6?) ; 0= ROM $100-$1F00 ; 1= ROM $160-$1F00 RAM $100-$160 SECUR = %00001000 ; SECURITY ENABLE BIT ; 1= ENABLE SECURITY ; 0= DISABLE SECURITY IRQRO = %00000010 ; INTERRUPT TRIGGER MODE ; 1= EDGE TRIGGERED ONLY IRQ ; 0= LEVEL & EDGE SENSITIVE .ENDIF @ENDNODE @NODE HC805C_PROM **************************** * PROGRAMMING REGISTERS * **************************** .IFD HAS_PROM8 ; HC805C4 ONLY PR = REGS+$1C ; EEPROM PROGRAMMING REGISTER CPEN = %01000000 ; CHARGE PUMP ENABLE ; *0= CHARGE PUMP SWITCHED OFF ; 1= CHARGE PUMP POWER SWITCHED ON ERASE = %00001000 ; ERASE/NORMAL CONTROL OF EEPROM ; *0= NORMAL READ OR PROGRAM MODE ; 1= ERASE MODE LATA = %00000100 ; LATCH A ENABLE LATB = %00000010 ; LATCH B ENABLE EEPGM = %00000001 ; EEPROM PROGRAM COMMAND ; *0= PROGRAM (OR ERASE) POWER SWITCHED OFF ; 1= PROGRAM (OR ERASE) POWER SWITCHED ON ARL = REGS+$1D ; HARDWARE BREAKPOINT REGISTER LOW ARH = REGS+$1E ; HARDWARE BREAKPOINT REGISTER HIGH MATCH = %00100000 ; ENABLE HARDWARE BREAKPOINT ; *0= BREAKPOINT DISABLED ; 1= BREAKPOINT ENABLED IRQRO = IRQS-1 ; IRQ OPTION REGISTER ($1FDF) IRQE = %00000010 ; IRQ SELECT EDGE SENSITIVE ONLY ; 1= IRQ CONFIGURED FOR LOW LEVEL ; & FALLING EDGES TRIGGER ; 0= IRQ CONFIGURED FOR FALLING EDGES ; TRIGGER ONLY .ENDIF @ENDNODE