@DATABASE
@NODE MAIN 6804
* 6804 HyperSource© include file for 6804
* © 1998 RST Ralf Steines Trier, ALL RIGHTS RESERVED
*
* source: as1406 include file
*

    @{" 6804 MEMORY        " link "6804_MEMORY"}
    @{" 6804 CPU-CORE      " link "6804_CPU-CORE"}
    @{" 6804 INTERRUPTS    " link "6804_INTERRUPTS"}

    @{" 6804 IO-PORTS      " link "6804_IO-PORTS"}

    @{" 6804 TIMERS        " link "6804_TIMERS"}

* THIS INCLUDE FILE IS INCOMPLETE, I NEED MANUAL FIRST

@ENDNODE
@NODE 6804_MEMORY
****************************
*        MEMORY MAP        *
****************************

; ?? port lines, ?? pins

  REGS      = $0000    ;   16 BYTES REGS   $00-1F
                       ;   96 BYTES REGS   $A0-FF

  ROM0_BOT  = $0020    ;
  ROM0_SIZE = $0040    ;   64 BYTES ROM
  ROM0_TOP  = $0060    ;

  RAM_BOT   = $0080    ;
  RAM_SIZE  = $0030    ;   48 BYTES RAM
  RAM_TOP   = $00A0    ;

  ROM_BOT   = $0100    ;
  ROM_SIZE  = $1000    ; 3840 BYTES ROM  ?????
  ROM_TOP   = $0000    ;

  IRQS      = $0FF8    ;    8 BYTES IRQS

@ENDNODE
@NODE 6804_INTERRUPTS
****************************
*    INTERRUPT VECTORS     *
****************************

  V_RES     = IRQS+$06 ;


@ENDNODE
@NODE 6804_CPU-CORE
************************
*       CPU CORE       *
************************

* I'M NOT SHURE IF EVERY 6804 SUPPORTS THE STOP/WAIT INSTRUCTIONS.
* IF YOU FIND ANY THAT DOESN'T TELL ME, AND I MAKE THEM SWITCHABLE.

* THESE REGISTER EQUATES ARE ALREADY DONE IN THE RELATING CPU LIBRARY,
* AND ARE JUST DESCRIBED HERE FOR DOCUMENTATION.

; X         = REGS+$80 ;  X INDIRECT REGISTER
                       ;  (*UNDEFINED AFTER RESET)

; Y         = REGS+$81 ;  Y INDIRECT REGISTER
                       ;  (*UNDEFINED AFTER RESET)

; V         = REGS+$82 ;  SHORT ADDRESSING V REGISTER (NONE STANDARD NAME)
                       ;  (*UNDEFINED AFTER RESET)

; W         = REGS+$83 ;  SHORT ADDRESSING W REGISTER (NONE STANDARD NAME)
                       ;  (*UNDEFINED AFTER RESET)

; A         = REGS+$FF ;  ALU A REGISTER
                       ;  (*UNDEFINED AFTER RESET)


@ENDNODE
@NODE 6804_IO-PORTS
****************************
*   INPUT/ OUTPUT PORTS    *
****************************

* THE BIT DEFINITIONS ARE A GUESS AND MAY BE NONSENSE, TELL ME

  PORTA     = REGS+$00 ; PORT A DATA REGISTER
                       ;  (*UNDEFINED AFTER RESET)

        PA7       = %10000000   ; I/O
        PA6       = %01000000   ; I/O
        PA5       = %00100000   ; I/O
        PA4       = %00010000   ; I/O
        PA3       = %00001000   ; I/O
        PA2       = %00000100   ; I/O
        PA1       = %00000010   ; I/O
        PA0       = %00000001   ; I/O

  PORTB     = REGS+$01 ; PORT B DATA REGISTER
                       ;  (*UNDEFINED AFTER RESET)

        PB7       = %10000000   ; I/O
        PB6       = %01000000   ; I/O
        PB5       = %00100000   ; I/O
        PB4       = %00010000   ; I/O
        PB3       = %00001000   ; I/O
        PB2       = %00000100   ; I/O
        PB1       = %00000010   ; I/O
        PB0       = %00000001   ; I/O


  PORTC     = REGS+$02 ; PORT C DATA REGISTER
                       ;  (*UNDEFINED AFTER RESET)

        PC7       = %10000000   ; I/O
        PC6       = %01000000   ; I/O
        PC5       = %00100000   ; I/O
        PC4       = %00010000   ; I/O
        PC3       = %00001000   ; I/O
        PC2       = %00000100   ; I/O
        PC1       = %00000010   ; I/O
        PC0       = %00000001   ; I/O

  DDRA      = REGS+$04 ; DATA DIRECTION REGISTER FOR PORT A

        DDA7      = %10000000   ; *0=IN 1=OUT
        DDA6      = %01000000   ; *0=IN 1=OUT
        DDA5      = %00100000   ; *0=IN 1=OUT
        DDA4      = %00010000   ; *0=IN 1=OUT
        DDA3      = %00001000   ; *0=IN 1=OUT
        DDA2      = %00000100   ; *0=IN 1=OUT
        DDA1      = %00000010   ; *0=IN 1=OUT
        DDA0      = %00000001   ; *0=IN 1=OUT

  DDRB      = REGS+$05 ; DATA DIRECTION REGISTER FOR PORT B

        DDB7      = %10000000   ; *0=IN 1=OUT
        DDB6      = %01000000   ; *0=IN 1=OUT
        DDB5      = %00100000   ; *0=IN 1=OUT
        DDB4      = %00010000   ; *0=IN 1=OUT
        DDB3      = %00001000   ; *0=IN 1=OUT
        DDB2      = %00000100   ; *0=IN 1=OUT
        DDB1      = %00000010   ; *0=IN 1=OUT
        DDB0      = %00000001   ; *0=IN 1=OUT

  DDRC      = REGS+$06 ; DATA DIRECTION REGISTER FOR PORT C

        DDC7      = %10000000   ; *0=IN 1=OUT
        DDC6      = %01000000   ; *0=IN 1=OUT
        DDC5      = %00100000   ; *0=IN 1=OUT
        DDC4      = %00010000   ; *0=IN 1=OUT
        DDC3      = %00001000   ; *0=IN 1=OUT
        DDC2      = %00000100   ; *0=IN 1=OUT
        DDC1      = %00000010   ; *0=IN 1=OUT
        DDC0      = %00000001   ; *0=IN 1=OUT


@ENDNODE
@NODE 6804_TIMERS
****************************
*     TIMER REGISTERS      *
****************************

  * THESE REGISTERS HAVE TO GET DESCRIBED COMPLETELY

  TSCR      = REGS+$09 ; TIMER STATUS AND CONTROL REGISTER

  TCR       = REGS+$FE ; TIMER COUNTER REGISTER

  TPR       = REGS+$FD ; TIMER PRESCALER REGISTER

@ENDNODE