; speedychip.ASM  --  v1.0.6 5.11 1997
; Patch to speed up chipmem writeaccess on 060 CPUs.
; Tested with BLIZZARD 1260, Apollo 4060 and CS MK II 060.
; Written by Harry "Piru" Sintonen <sintonen@jyu.fi> (IRC: Piru).
; Copyright © 1997 Harry Sintonen. Freeware.
;
; This program was developed 22nd August while on IRC and was written
; using pico 2.9 ;) It was DCC'd on irc to Sly who compiled and tested
; it on his 1260. Also thanks a lot to Sly for sending me lots of 060
; MMU-list dumps... =) Thanks to Peeri for testing this on his A4000/060.
; Also thanks to Duken for testing this on A4000/CS060. 5.11: RobinC
; succesfully tested speedychip on his Blizzard 1260. Finally tests only
; for 060. RobinC compiled 1.0.6, thanks dude!-)
;
; This routine can be used for any purpose (for demos too, hehe:), but you
; should give me some credit... (or? I don't think this is unreasonable).
; Note that this patch needs to be started after SetPatch.
;
; Apparently daeron has made this before, but I wanted to see how much
; this speeds things up. I also wanted to learn something about 040/060
; MMU (I have 030). Yet one funny thing: I didn't use Amiga at all when I
; wrote this program:))
;
; I've also heard that there is program called SetCacheMode by Phase5. No
; one seems to have it tho ;). Anyways, speedychip doesn't base on it.
;
; Oh, and one thing: I take no responsibility for damages caused by these
; 1'n'0s... ;)
;

	include	"exec/types.i"
	include	"exec/libraries.i"
	include	"exec/execbase.i"
	include	"exec/exec_lib.i"

call	MACRO
	jsr	(_LVO\1,a6)
	ENDM

Main	move.l	(4).w,a6
	tst.b	(AttnFlags+1,a6) ; Test for 060 (bit 7)
	bmi.b	.has_060p
	moveq	#60,d0		;)
	rts

.has_060p
	lea	(.gettcr,pc),a5
	call	Supervisor
	btst	#15,d0		; E - Enable
	bne.b	.mmu_enabled
	moveq	#20,d0		; 68060.library not loaded... (run SetPatch)
	rts

.mmu_enabled
	btst	#14,d0		; P - Page Size
	beq.b	.has4k		; Must have 4k page size
	moveq	#20,d0
	rts

.has4k	call	Disable		; no others messing around, please...

	lea	(.geturp,pc),a5
	call	Supervisor
	move.l	d0,a0		; a0=array of 128 root-level table descriptors, 32mb each

	move.l	(a0),d0
	and.w	#$FE00,d0
	move.l	d0,a4		; a4=array of 128 pointer table descriptors, 256k each

	moveq	#8-1,d3		; Patch all page desciptors of first 8 table
.mloop	move.l	(a4)+,d0	; descriptors (8*256k=2m=size of chipmem)
	bsr.b	.patch
	dbf	d3,.mloop

	lea	(.flush,pc),a5	; flush ATC & caches
	call	Supervisor
	call	CacheClearU	; flush caches with OS too (just to be sure:)
	call	Enable		; and back...

	moveq	#0,d0		; all ok!
	rts

.patch	and.w	#$FE00,d0
	move.l	d0,a0		; a0=array of 64 page descriptors
	moveq	#64-1,d1
.ploop	move.l	(a0),d2
	move.l	d2,d0
	and.b	#%11,d0		; get PDT
	beq.b	.next		; 00=invalid
	cmp.b	#%10,d0		; 10=indirect
	beq.b	.next

	; ok this is really it:

	or.b	#%1100000,d2	; set cm (bits 5&6) to 11 (Cache-Inhibited, Imprecise exception model)
	move.l	d2,(a0)

.next	addq.l	#4,a0
	dbf	d1,.ploop
	rts

.gettcr	dc.l	$4e7a0003	;movec	tc,d0
	nop
	rte

.geturp	dc.l	$4e7a0806	;movec	urp,d0
	nop
	rte

.flush	dc.w	$F518	; PFLUSHA	flush the address translation cache
	dc.w	$F4F8	; CPUSHA BC	flush the caches into memory
	dc.w	$F4D8	; INVA  BC	invalidate the data and inst caches
 	nop
	rte

	dc.b	'$VER: speedychip 1.0.6 (5.11.97)',0
	dc.b	'$COPYRIGHT: Copyright © 1997 Harry "Piru" Sintonen <sintonen@jyu.fi>',10
	dc.b	'Freeware.',0