UISA, VEA, OEA

These are the three operating modes of the PowerPC. They can be
ordered in the following way:

UISA is a part of the VEA, which is a part of the OEA. This means 
that the OEA defines the entire PPC architecture, while both VEA 
and UISA define a part of it. UISA defines a part of the VEA.

UISA stands for User Instruction Set Architecture, which is equal 
to the user-level of the MC680x0 CPUs. This means that you are 
able to run all non-supervisor-level instructions in this mode.
Supervisor-level is often referred to as the 'priviliged' level
of a processor.


The following registers belong to the UISA


GPRs (General Purpose Registers) 0-31

 32 registers which are 32-bits in 32-bits-mode and 64-bits in
 64-bits-mode. Can be used for general purpose.

FPRs (Floating Point Registers) 0-31

 32 64-bits registers for Floating Point data.

Conditon Register

 32-bits register with 8 condition register fields:

         CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7

 all being 4 bits in size. The 4-bits are defined as follows:

      LT GT EQ SO
 bit   0  1  2  3 

 where LT = negative result
       GT = positive result
       EQ = zero
       SO = Copy of XER[SO] bit

Floating Point Status and Control Register (FPSCR)

 32-bits register with all the FPU exceptions and control tags

XER Register (XER)

 32-bits register:

     SO OV CA | 00000000 |     Byte Count
 bit  0  1  2 | -------- | 25 26 27 28 29 30 31

 where SO = Summary Overflow (STICKY, not automatically cleared)
       OV = Overflow
       CA = Carry

Link Register (LR)

 64/32-bits address register, mainly for use with branching 
 instructions

Count Register (CTR)

 64/32-bits address register, mainly for use with conditional
 branching instructions. (For example: CTR automatically 
 decrements at every 'dbcc' and program continues when CTR=0)


The following registers belong to the VEA:


All registers of the UISA.

TBL/TBU (2x32 bits)

 Time Base Register Low and High, contains periodically
 incremented value for use with timing etc.. However, this
 register is implementation-dependent, which means it may
 operate completely different on different implementations...

 You can simply read both of them in rA:rB by using:

 smovec   TBR,rA:rB

 Both the VEA and OEA instruction-set and registers can 
 only be accessed in supervisor-mode!


The following register belong to the OEA:


All registers of the UISA and VEA.

Machine State Register - MSR

 Contains configuration of the PPC operating mode.

Processor Version Register - PVR

 Contains the ID of the processor

All MMU and Exception registers

Time Base Write and Decrementer register