Some General Information About The Software And The Hardware. ------------------------------------------------------------- Introduction:- -------------- The following information in this document will be split up into four detailed parts:- 1) The bad points in my circuit design(s). Bits that were omitted due to many reasons, the main ones being cost and complexity. 2) The full circuit description of the Oscilloscope. 3) The bad points about my software. 4) The software itself and some extracts from the software enabling me to access the parallel port at high speed. I am a professional ~RF~ Electronics Engineer and I am well aware of the limitations of my circuit design(s). I am also a self taught programmer (coder) and do not follow the same rules that professional software engineers follow. Note also that most of the components for this project were salvaged from the ~Junk Box~ and NOT purchased at all. Now read on.... ---------------------------------------------------------------------------- Part 1): The bad points of my circuit design(s). ------------------------------------------------ For the first part I will refer to the ~Scope_Circuit_1B.drawing~. ------------------------------------------------------------------ There are only two major shortfalls in ~Scope_Circuit_1B~ and these are as follows:- 1) The internal regulator of the A-D Converter (IC1) is connected to the unregulated positive (+9 Volts) battery rail. As the battery goes flat (discharges and becomes exhausted) the voltage at the battery's terminals drop. This affects the voltage at Pin 4 of IC1. As the dynamic impedance of this Voltage Reference is around 12 Ohms this results in small variation in the regulated voltage at Pin 4. This will give rise to another minor problem, see 3). 2) C5 is an Electrolytic Capacitor placed accross the +5 Volt regulated rail. This is to help decouple and reduce any LF (Low Frequency) noise in the +5 Volt supply generated by a poor quality regulator IC (IC3). This capacitor has a relatively large internal inductance and is unable to reliably filter out unwanted HF (High Frequency) noise. I have NOT included a parallel capacitor of around 47nF to do this task as my prototype was relatively free from this problem. 3) This is a follow on from 1). As the regulated voltage at Pin 4 slowly goes lower over a period of time, the DC Offset Point at Pin 11 of IC1 changes. This produces part of the error in the DC Stability specifications. Also as the DC Levels fall the Signal/Noise Ratio of the IC become worse. However this is very minor and is really only of academic interest. For the second part I will refer to the ~Scope_Circuit_2.drawing~. ------------------------------------------------------------------ There is only one thing to look out for in this part of the construction, and that is poor quality regulator ICs. These are known to generate LF (Low Frequency) random noise in the range of DC to 1KHz. This noise can inject itself into sensitive parts of an electronic ciruit. Because the output impedance of a typical regualtor IC is low this noise is not easy to filter out. Discrete component regulated supplies are much better for this reason but cost more money and are harder to construct. For the third part I will refer to the ~Scope_Circuit_3A.drawing~. ----------------------------------------------------------------- There are several things that should have been put into the design but were NOT due to cost and complexity, these are as follows:- 1) Starting with Gate of Q5, there are two Back to Back 1N4148 small signal silicon diodes connected between the Gate and Ground. If these are fitted (they are optional) to protect the input circuit from high voltage overloads then they WILL generate a small amount of random noise. This WILL affect the overall Signal/Noise Ratio of the DC Amplifier. My prototype was about 50dB which I considered to be OK. 2) Temperature compensation of Q5 could have been added using a MATCHED 2N3819 of which the IDSS characteristic was the same as Q5 and placed into the Source circuit of Q5 as a constant current source. This was NOT added due to cost and increased complexity. 3) Temperature compenstaion of Q6 and Q7 due to VBE characteristics were also NOT designed in and hence adding to the poor ~Temperature Stability~ specifications. This was also because of cost and complexity. 4) The constant current source Q8 is fed via two diodes 1N400x. This is used to set the quiescent current in the circuit and hopefully reject any HF noise in the supply rail. Because the internal impedance of these two diodes and the VBE charasteristic of Q8 vary with temperature the quiescent current will have a small variation. This will affect the ~DC Stability~ specifications. This was also due to cost of MATCHED devices. 5) Temperature compenstaion of Q9 could have been cured probably with a simple thermistor accross R32 but as I did NOT have one in the ~Junk Box~ I did NOT pursue it any further as the stage gain of this section is only about 22dB and probably would not suffer the problem. 6) C17 is an Electrolytic Capacitor of 22uF which is in series with R28 a 10 KilOhm Resistor. The time constant is fairly large so that the settling time of the overall amplifier to come to a stable DC condition could be long. Hence it is wise to allow at least 10 Minutes for the whole unit to come to operating voltage and temperature before use. For the last part I will refer to the ~Scope_Circuit_4.drawing~:- ----------------------------------------------------------------- 1) All of the relays were 6 Volt coil types (NOT 5 Volt coils), as these were cheap. They all energised and switched over properly in the prototype but you could find that if you use these 6 Volt relays, they will NOT change over properly when testing your project. You will therefore have to source 5 Volt coil types if necessary. The Input Attenuator resistors R33 to R44 inclusive have NOT got parallel compensation capacitors added for frequency compensation as the bandwidth was only approximately 100KHz and I decided that NONE were required. ---------------------------------------------------------------------------- Part 2): The Circuit Description. --------------------------------- Now that I have pointed out the majority of the failings of my circuit design(s) let us go onto the description of the SIMPLE ciruits proper. Starting with the ~Scope_Circuit_1B.drawing~:- ---------------------------------------------- Q2 is fed from one of the AMIGAs parallel port control lines through R1, a 10 KilOhm Resistor. When this line goes high (the DC button on the ~Scope~ software), Q2 conducts and the relay RLA energises to short out C1 and C2. This will connect the front end of the Input Attenuator Circuit directly to the input socket and set the whole amplifier to a DC state. When this control line goes low (the AC button on the ~Scope~ software), Q2 stops conducting and RLA de-energises to reset the Input Attenuator Circuit back to AC coupling. D2 and R8 provide a positive rail backup in the event of the +5 Volt supply failing for any reason. Under normal operation there will be NO current drawn from the AMIGA's parallel port Pin 14. This is provided to protect IC1 from having any unwanted negative voltages appearing on it at all. R5 and R6 feed the parallel port's D6 and D7 data lines to give an indication of either or both of the batteries becoming exhausted (flat). ~A~ and ~B~ are connected to the low battery detect circuits of ~Scope_Circuit_2.drawing~. RV1 sets the position of the Reference Ladder of the A-D Converter. Any HF noise is reduced by C6, LF noise was NOT a problem. Q1 provides a low impedance source for the VREF input circuit of IC1, (Pin 9). The A-D Converter IC is clocked in real time via the ~STROBE~ line and NOT by a seperate oscillator. Because the IC is clocked at a MUCH slower rate than it is capable of this improved the internal Signal/Noise Ratio of the IC. C8 and R9 provided a simple Reset Circuit to the IC for a Cold Startup only. The A-D Converter B1 to B6 lines are connected to the data lines D0 to D5 of the parallel port respectively. As the Overflow line (Pin 2 of IC1) is not used, it was left disconnected. D3B is shown short circuited, this is an optional item and its use is described in the ~Manual~. As the ~STROBE~ line pulse width is about 1.5uS wide and the rise time and slew rates are approximately 1uS each this set an upper limit to the port access. I decided that 200KHz was fast enough so I based my design around this. Now onto the ~Scope_Circuit_2.drawing~:- ---------------------------------------- When all of the supply rails are working properly Q3 and Q4 are both in a conducting state. Q3 clamps ~A~ to ground and Q4 clamps ~B~ to ground, D4 and D5 protect line ~B~ from going negative and damaging the AMIGA's parallel port. As the voltages from the batteries falls either or both ZD1 and ZD2 stop conducting and switches either or both Q3 and Q4 off sending lines ~A~ or ~B~ high. This change is detected by the software and can be read from the ~On Line Help~ file of the ~Scope~ program. R16 and R18 are selected to give a transition at about +7 Volts for the positive rail and about -7 Volts for the negative rail. IC2 provides the regulated negative rail and IC3 the regulated positive rail. C9 to C14 inclusive provide the majority of any decoupling required. Now onto the ~Scope_Circuit_3A.drawing~:- ----------------------------------------- Also refer to the ~Scope_Circuit_4.drawing~, D8, D9 and R25 provide some degree of protection to the Gate input of the FET Q5 (2N3819). Q5 is a Source follower where R24 and R23 provide a potential divider to set the Base of Q6 negative with respect to ground. Q6 and Q7 form a simple ~Long Tailed Pair~ of which the stage gain is set by RV3 and R19. R20 and R21 provide a degree of current negative feedback to improve the linearity of the overall amplifier. Q8 and its' associated circuitry is a constant current source and provides the quiescent current through Q6 and Q7. This is adjusted using RV4. The Base of Q7 is fed from the potential divider R29, RV2 and R30 thorugh R28 decoupled by C18, C16 and C17. RV2 sets the DC conditions at the Collector of Q7 and hence Q9, and the input of IC1. C21 is optional and provides an HF roll off at approximately 100KHz. It also helps in reducing HF noise. R27 is connected between Q7 Collector and Q9 Base to prevent any parasitic oscillations that may occur in the amplifier. R32 provides a degree of current negative feedback for Q9 and also helps to improve linearity. Adequate decoupling for the front end is achieved using L1, L2, C7, C15, C22 and C23. The diode D3A shown on ~Scope_Circuit_1B.drawing~ is to prevent the input of IC1 from going negative by more than 0.5 Volts when Q9 is in a NONE conducting state. Because the reverse polarity capacitance is small in these diodes, it does NOT affect the overall bandwidth of the DC Amplifier. And finally the ~Scope_Circuit_4.drawing~:- ------------------------------------------- J1 (a BNC socket), is connected to the RLA1 and RLA2 relay switching contacts using high quality coaxial cable. A return coaxial cable is connected to the Input Attenuator which comprises of 1% tolerance resitors wired in series to give an overall Input Resistance of 1 MegOhm. The Input Capacitance was estimated at between 45pF and 55pF, thus giving the 56pF value in the specifications. When NO power is applied to the ~Scope~ board the relays are all denergised as shown in the drawing. However upon powering up with the AMIGA, and the ~Scope~ software NOT running, RLI energises and sets the Input Sensitivity to 30V/DIV. Upon starting the ~Scope~ software the relays count down from 30V/DIV to the required range. This uses a Divide By 8 Johnson Counter IC and is Reset and Clocked from two of the control lines of the parallel port. At the same time the Input Mode is set to AC. This condition ALWAYS occurs everytime the Vertical Sensitivity is accessed. The relay common contacts are wired in parallel to give a common output. This is connected to the input of Q5 via R25. When the ~Scope Board~ is running normally, there will ONLY be a MAXIMUM of two relays energised, ALWAYS one Input Attenuator relay, and the Input Mode relay when set to DC mode. Therefore the total current draw on the positive rail will be approximately 120mA. The negative rail current draw will be of the order of approximately 10mA. This puts a limit of battery life on the positive rail to about 12 hours, and on the negative rail to about 120 hours. It is wise therefore to swap the batteries over to discharge them evenly. ---------------------------------------------------------------------------- Part 3): My poor programming techniques. ---------------------------------------- As I do NOT intend to issue the Source Code yet, (YES, I will issue it eventually) I will disclose my bad habits in programming techniques. 1) As I do NOT trust compilers of ANY kind I write in either/or BASIC (usually the ACE/AIDE combination) and assembler. 2) Any of my BASIC is SIMPLE and I mean SIMPLE, this includes using the LET statement. Some coders laugh at this but if the software works and the Source Code is easily readable then why not. 3) I do NOT structure any of my programs. 4) I do NOT trust jumping to SUBROUTINES and only use for example the GOSUB/RETURN only if I have to. 5) All of my CONDITIONAL jumps are SIMPLE. 6) I try to make the whole package as OS friendly as possible. 7) All of my programs are written to work on an A500, but uncalibrated. 8) The parallel port is opened up under WorkBench but is hit directly when I want to read from it. 9) That is all I can think of so far. ---------------------------------------------------------------------------- Part 4): Some extracts and aspects of the software. --------------------------------------------------- On program startup the parallel port is opened up to read from the data lines and write to the control lines as required. This is done using machine code and under the control of the OS. The variables are all set up using compiled BASIC and all of the user interfaces are set up using compiled BASIC. Compiled BASIC is used to set up the hardware through the parallel port using the POKE statement, there is no need to do this using machine code. When the real time access is required this is done using minimal assembler coding, an extract is shown below:- REM Assembly subroutine to aquire the parallel port here. REM OK. ASSEM movem.l d0-d7/a0-a6,-(sp) ;Save all registers. lea.l $address,a0 ;Load my storage address. move.l (a0),a0 ;The contents of this address point ;to my 64KB memory "store". move.l a0,d1 ;Place this into d1 register. movea.l $4,a6 ;Move "Exec" pointer to a6. jsr -132(a6) ;Disable tasking. jsr -120(a6) ;Disable interrupts. ;These two values have NOT changed ;since the early days of the AMIGA. move.l #0,d0 ;Clear d0 for use, do NOT use the ;"clr.l d0" instruction. move.w #$ffff,d2 ;64KB counter. ;-----------------------------------------Start of port access. port_access_routine: move.l d1,-(sp) ;Push "store" onto the stack. move.b $bfe101,d0 ;Read the parallel port. NOTE that ;the ~STROBE~ line is clocked ;automatically by the system. andi.b #$3f,d0 ;Ensure the bottom 6 bits only. move.l (sp)+,a0 ;Pop the "store" back into a0. move.b d0,(a0) ;Put d0's value into the "store". add.l #1,d1 ;Increase "store" by one position. dbf d2,port_access_routine ;Do until counter is finished. ;-----------------------------------------Finish of port access. movea.l $4,a6 ;Move "Exec" pointer to a6. ;This is a double check only. jsr -126(a6) ;Enable interrupts. jsr -138(a6) ;Enable tasking. ;These two values have NOT changed ;since the early days of the AMIGA. movem.l (sp)+,d0-d7/a0-a6 ;Reload all registers. EVEN END ASSEM REM Assembly routine ends here. This will clock the ~STROBE~ line at approximately 200KHz. Does anyone know of a quicker routine? If you do then please contact me on my Email address. ---------------------------------------------------------------------------- Below is an extract of the plotting of the trace to the screen using my very rare GOSUB/RETURN statements written in ACE Basic Compiler. REM OK. rescan: GOSUB clear_window: COLOR brightness,2 LINE STEP (n,(shift-(waveform-31)*multiplier))-(14,(shift-(waveform-31)*multiplier)),2 LET n=14 REM This address 12574977 is the parallel port. start_frame: IF timebase_range<=3 THEN GOSUB direct_port_access: IF timebase_range>3 THEN GOSUB indirect_port_access: LET n=n+1 IF n>173 THEN GOTO next_frame: GOTO start_frame: next_frame: LET a$=INKEY$ IF a$=CHR$(13) OR single_shot=1 THEN GOTO aquire_exit: GOTO aquire_trace1: aquire_exit: IF graticule=1 THEN GOSUB set_graticule: GOTO main_loop: REM This is the routine for the bottom 3 timebase ranges. REM OK. direct_port_access: LET slow_range_delay=1 slow_delay: LET waveform=PEEK(12574977) REM Do NOT remove this line at all. IF waveform>=63 THEN LET waveform=63 IF n=14 THEN LINE STEP (n,(shift-(waveform-31)*multiplier))-(n,(shift-(waveform-31)*multiplier)),2 IF n=15 THEN LINE STEP (n,(shift-(waveform-31)*multiplier))-(n,(shift-(waveform-31)*multiplier)),2 LINE STEP (n,(shift-(waveform-31)*multiplier))-(n,(shift-(waveform-31)*multiplier)),brightness LET slow_range_delay=slow_range_delay+1 IF slow_range_delay>=timebase_calibrate THEN GOTO delay_exit: GOTO slow_delay: delay_exit: RETURN REM This is the routine for the top 3 timebase ranges. REM OK. indirect_port_access: LET waveform=PEEK(waveform_address&) REM Do NOT remove this line at all. IF waveform>=63 THEN LET waveform=63 IF n=14 THEN LINE STEP (n,(shift-(waveform-31)*multiplier))-(n,(shift-(waveform-31)*multiplier)),2 IF n=15 THEN LINE STEP (n,(shift-(waveform-31)*multiplier))-(n,(shift-(waveform-31)*multiplier)),2 LINE STEP (n,(shift-(waveform-31)*multiplier))-(n,(shift-(waveform-31)*multiplier)),brightness LET waveform_address&=waveform_address&+timebase_calibrate RETURN ============================================================================ IMPORTANT:- ----------- The Legal Stuff:- ----------------- These programs are the copyright of (C)2001 Barry Walker with all rights reserved. They are freeware and no profit will be made from them, also all of the files must remain unaltered and intact including this one. The author is not responsible for any damage to, or loss of, or failure of equipment or data caused in any way by the use of these programs. ---------------------------------------------------------------------------- Contact:- --------- Mr Barry Walker, 70 King George Road, Loughborough, Leicestershire, LE11 2PA, England. Email to:- wisecracker@tesco.net BYE..... ============================================================================