;
; Cache.S - set caches properly. Taken from kick2.04 ROM.
; Use as Exec/CacheControl() function.
;
;
;
; old state  =CacheControl( bits, mask )
; d0                        d0    d1
;

**
**  Bit Definition Macro
**
**  Given:
**	BITDEF	MEM,CLEAR,16
**
**  Yields:
**	MEMB_CLEAR  EQU 16			; Bit number
**	MEMF_CLEAR  EQU 1<<16			; Bit mask
**

BITDEF	    MACRO   ; prefix,&name,&bitnum
	    BITDEF0 \1,\2,B_,\3
\@BITDEF    SET     1<<\3
	    BITDEF0 \1,\2,F_,\@BITDEF
	    ENDM

BITDEF0     MACRO   ; prefix,&name,&type,&value
\1\3\2	    EQU     \4
	    ENDM


******* Selected bit definitions for Cache manipulation calls **************

	BITDEF	CACR,EnableI,0		;Enable instruction cache
	BITDEF	CACR,FreezeI,1		;Freeze instruction cache
	BITDEF	CACR,ClearI,3		;Clear instruction cache
	BITDEF	CACR,IBE,4		;Instruction burst enable
	BITDEF	CACR,EnableD,8		;68030 Enable data cache
	BITDEF	CACR,FreezeD,9		;68030 Freeze data cache
	BITDEF	CACR,ClearD,11		;68030 Clear data cache
	BITDEF	CACR,DBE,12		;68030 Data burst enable
	BITDEF	CACR,WriteAllocate,13	;68030 Write-Allocate mode (must
					;always be set)
	BITDEF	CACR,CopyBack,31	;Master enable for copyback caches


	BITDEF	DMA,Continue,1		;Continuation flag for CachePreDMA
	BITDEF	DMA,NoModify,2		;Set if DMA does not update memory


******************************************************************************
*
*
*

F80C4C:	movem.l	d2-d4/a5,-(a7)
	moveq	#0,d3
	move.w	$128(a6),d4	; Execbase->AttnFlags
	btst	#1,d4
	beq.s	F80C6C
	and.l	d1,d0
	ori.w	#$808,d0
	not.l	d1
	lea	F80C74(pc),a5
	jsr	-$1E(a6)	; _LVOSuperVisor
F80C6C:	move.l	d3,d0
	movem.l	(a7)+,d2-d4/a5
	rts

F80C74: ori.w	#$700,sr
	movec	cacr,d2		; $4E7A2002
	btst	#3,d4
	beq.s	F80C88
	swap	d2
	ror.w	#8,d2
	rol.l	#1,d2
F80C88:	move.l	d2,d3
	and.l	d1,d2
	or.l	d0,d2
	btst	#3,d4
	beq.s	F80CA4
	ror.l	#1,d2
	rol.w	#8,d2
	swap	d2
	andi.l	#$80008000,d2
	nop
	cpusha	bc		; $F4F8
F80CA4:	nop
	movec	d2,cacr		; $4E7B2002
	nop
	rte