A i l Presents 68000 Assembly Language For Beginers 1. 68000 Architecture Data Registers. --------------- D0 - D7 Address Registers. ------------------ A0 - A7 The Stack. ---------- Move.L D0,-(A7) * A "Push" Operation Move.L (A7)+,D0 * A "Pop" Operation The Status/Condition Code Register ---------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | T| | S| | |I2|I1|I0| | | | X| N| Z| V| C| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Fig.1-1 :Status/Condition Code Register T: 1 = Trace Mode S: 1 = Supervisor State I2,I1,I0: Interrupt Mask X: eXtend Flag N: Negative Flag Z: Zero Flag V: oVerflow Flag C: Carry Flag Memory Data Formats ------------------- Byte data - 1 Byte = 8 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |msb Byte 0 | Byte 1 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | Byte 2 | Byte 3 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Word Data - 1 Word = 16 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |msb Word 0 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | Word 1 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | Word 2 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Longword Data - 1 Longword = 32 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | | + + + + + + + Longword 0 + + + + + + | | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | | + + + + + + + Longword 1 + + + + + + | | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | | + + + + + + + Longword 2 + + + + + + | | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ BCD Data - 2 BCD Digis = 1 Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |msd BCD 0 | BCD 1 lsd| BCD 2 | BCD 3 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | BCD 4 | BCD 5 | BCD 6 | BCD 7 | +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Fig 1-2 : Data Organization In Memory The Memory Map -------------- Vector Address Assignment ------ ------- ---------- 0 000 Reset Initial Supervisor Stack Pointer 004 Reset Initial Program Counter 2 008 Bus Error 3 00c Address Register 4 010 Illegal Instruction 5 014 Divide-By-Zero 6 018 CHK Instruction 7 01c TRAPV Instruction 8 020 Privilege Viqlation 9 024 Trace 10 028 Op Code 1010 11 02c Op Code 1111 12 030 Reserved 13 034 Reserved 14 038 Reserved 15 03c Uninitialized Interrupt Vector 16-23 040-05c Reserved 24 060 Supurious Interrupt 25 064 Level 1 Interrupt Autovector 26 068 Level 2 Interrupt Autovector 27 06c Level 3 Interrupt Autovector 28 070 Level 4 Interrupt Autovector 29 074 Level 5 Interrupt Autovector 30 078 Level 6 Interrupt Autovector 31 07c Level 7 Interrupt Autovector 32-47 080-0bc TRAP Instruction Vector 48-63 0c0-0fc Reserved 64-255 100-3ff User Definable Interrupt Vectors Fig 1-3 Exception Vector Tabel 2. Addressing Modes The Effective Address --------------------- Move.W , Move.W = Move Word Data Register Direct -------------------- Move.L Dn,Dn Move.L = Move Longword n = Register Number 0-7 Address Register Direct ----------------------- Move.L An,An n = Address Register 0-7 Address Register Indiect ------------------------ Move.s (An),(An) s = Byte ,Word ,Longword n = Address Register 0-7 Address Register Indirect With Postincrement -------------------------------------------- Move.B (An)+,(An)+ n = Address Register 0-7 Address Register Indirect With Predecrement ------------------------------------------- Move.B -(An),-(An) n = Address Register 0-7 Address Register Indirect With Displacement ------------------------------------------- Move.B d(An),d(An) n = address Register 0-7 d = Memory Location (F.ex. $ 4000) Address Register Indirect With Index ------------------------------------ Move.B d(An,Xn.s),Dn d = Memory Location (F.ex. $ 4000) n = Address (Or Data) Register 0-7 X = Data Or Address Register (F.ex D0 or A0) s = Longword or Word (.L or .W) Absolute Short Address ---------------------- Move.B xxx.W,Dn xxx = Memory Address n = Data Register 0-7 Absolute Long Address --------------------- Move.B xxx.L,Dn xxx + Memory Address n = Data Register 0-7 Program Counter With Displacement --------------------------------- Move.B d(pc),Dn *Moves Pc + d To Dn d = Memory Address n = Data Register Program Counter With Index -------------------------- Move.B d(PC),Xn.s),Dn d = Memory Address X = Data Or Address Register n = Data/Address Register 0-7 s = Word Or Longword (.W or .L) Immediate Data -------------- Move.L #$xxx,An (Sometimes #Xn) xxx = Memory Location n = Address Register 0-7 X = Data Or Address Register Status Register And Condition Code Register Addressing ------------------------------------------------------ ANDI = And Immediate EORI = Exclusive Or Immediate ORI = Or Immediate 3.Data Transfer Instructions Note = Every Address On The List Below The MOVE Instruction -------------------- Assembler Syntax: Move.B , Move.W , Move.L , Examples Of MOVE: Move.W A0,D0 Move.B (A0),D0 Move.L #$1000,$FF00 Move.L A0,-(A7) Condition Flags Affected: N Set If The Data Transferred Is Negative, Otherwise Cleared Z Set If The Data Transferred Is Zero, Reset Otherwise V Always Cleared C Always Cleared X Not Affected Addressing Modes Allowed: Source: Dn An (An) (An)+ -(An) d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,Xn) #xxx Destination Dn (An) (An)+ -(An) D(An) d(An,Xn) xxx.W xxx.L Move To CCR Instruction (Move To Condition Code Register) --------------------------------------------------------- Assembler Syntax: Move.W , Examples Of Move To CCR: Move.W #0,CCR Move.W (A7)+,CCR Condition Flags Affected: N Set To Bit 3 Of The Source Operand Z Set To Bit 2 Of The Source Operand V Set To Bit 1 Of The Source Operand C Set To Bit 0 Of The Source Operand X Set To Bit 4 Of The Source Operand Addressing Modes Allowed: Source Dn d(An) (An)+ -(An) d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,Xn) # xxx Move To SR Instruction (Move To Status Register) ------------------------------------------------ Assembler Syntax: Move.W ,SR Examples Of Move To SR: Move.W #$2700,SR Move.W (A7)+,SR Condition Flags Affected: Set To The Source Operand Low Byte. Addressing Modes Allowed: Source Dn (An) (An)+ -(An) d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,Xn) # xxx Move From SR Instruction ------------------------ Assembler Syntax: Move.W SR, Examples Of Move Form SR: Move.W SR,$FF00 Move.W SR,-(A7) Condition Flags Affected: None Addressing Modes Allowed: Destination Dn (An) (An)+ -(An) d(An) d(An,Xn) xxx.W xxx.L Move USP Instruction (Move To/From User Stack Pointer) ------------------------------------------------------ Assembler Syntax: Move.L USP,An Move.L An,USP Example Of Move USP: Move.L USP,A0 Move.L A0,USP Condition Flags Affected: None Addressing Modes Allowed: An MoveA Instruction (Move Address) -------------------------------- Assembler Syntax: Move.W ,An Move.L ,An Examples Of MoveA: MoveA.W #$FFFF,A0 MoveA.L #$FFFF,A0 Condition Flags Affected: None Addressing Modes Allowed: Source Dn An (An) (An)+ -(An) d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,Xn) # xxx MoveM Instruction (Move Multiple) --------------------------------- Assembler Syntax: MoveM.W , MoveM.W , MoveM.L , MoveM.L , Example Of MoveM: MoveM.L D0-D3,-(A7) MoveM.L D0/A0-A2,$FF00 Condition Flags Affected: None Addressing Modes Allowed: Source (An) (An)+ d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,Xn) Destination (An) -(An) d(An) d(An,Xn) xxx.W xxx.L MoveP Instruction (Move To/From Peripheral) ------------------------------------------- Assembler Syntax: MoveP Dn,d(An) MoveP d(An),Dn Examples Of MoveP: MoveP.L D0,0(A0) MoveP.W 0(A0),D0 Condition Flags Affected: None MoveQ (Move Quick) ------------------ Assembler Syntax: MoveQ #xxx,Dn Example Of MoveQ: MoveQ #2,D0 Condition Flags Affected: Set As For Move. LEA Instruction (Load Effective Address) ---------------------------------------- Assembler Syntax: LEA ,An Examples Of LEA: LEA 6(A6),A0 LEA 8(A6,D0.W),A0 Condition Flags Affected: None Addressing Modes Allowed: Source (An) d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,xn) Pea Instruction (Push Effective Address) ---------------------------------------- Assembler Syntax: PEA Example Of PEA: PEA 10(PC) PEA (A0) Condition Flags Affected: None Addressing Modes Allowed: Source (An) d(An) d(An,Xn) xxx.W xxx.L d(PC) d(PC,Xn) EXG Instruction (Exchange) -------------------------- Assembler Syntax: EXG Xn,Xn Examples Of EXG: EXG A0,D0 EXG D0,D1 Condition Flags Affected: None. Swap Instruction ---------------- Assembler Syntax: Swap Dn Examples Of Swap: Swap D0 Condition Flags Affected: N Set If Bit 31 Of The Result Is Set; Otherwise Cleared Z Set If THe 32-Bit Result Is Zero; Otherwise Cleared V Always Cleared C Always Cleared X Not Affected Link Instruction ---------------- Assembler Syntax: Link An,#xxx Examples Of Link: Link A6,#8 Condition Flags Affected: None UNLK Instruction (Unlink) ------------------------- Assembler Syntrax: UNLK An Examples Of UNLK: UNLK A6 Condition Flags Affected: None 4. Arithmetic Instructions