VeriWell for SPARC HDL     <Version 2.0.3b>    Sun Nov 24 10:20:03 1996

  This is a free version of the VeriWell for SPARC Simulator
  Distribute this freely; call 1-800-VERIWELL for ordering information
  See the file "!readme.1st" for more information

  Copyright (c) 1994 Wellspring Solutions, Inc.
            All rights reserved

Entering Phase I...
Compiling source file : pipealu.v
The size of this model is [85%, 69%] of the capacity of the free version

Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
   exercise
   oai21
   oi332
   ai332
   one

FREEZE cleared
UPCLOCK
     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 0, readdataout xxxx, aluresultout 0000
exmem: wbout 0, mout 0, pcaddout 0000, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout fffe, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0000, irout a505
newpc: 0002
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 0, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout fffe, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 0, mout 8, exout 2, pcout 0000, rd1out 0001, rd2out 0002, sextout 0005, instaout 1 instbout 2 instcout 0 idexout 5
ifid: pcout 0002, irout 0000
newpc: 0004
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 1, readdataout xxxx, aluresultout 0000
exmem: wbout 0, mout 8, pcaddout 000a, zeroout 0, overout 0, aluresout ffff, rd2out 0002, wdout 2 rtout 2
idex: wbout 1, mout 0, exout 5, pcout 0002, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0004, irout 0000
IfId Flush
IdEx Flush
ExMem Flush
newpc: 000a
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 0, readdataout xxxx, aluresultout ffff
exmem: wbout 0, mout 0, pcaddout 0002, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 0004, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 000a, irout 0000
newpc: 000c
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 0, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout 0004, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 000a, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 000c, irout 0571
newpc: 000e
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 1, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout 000a, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 000c, rd1out 0001, rd2out 0002, sextout fff1, instaout 1 instbout 2 instcout 7 idexout 0
ifid: pcout 000e, irout a4f8
newpc: 0010
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 1, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout ffee, zeroout 0, overout 0, aluresout 0003, rd2out 0002, wdout 7 rtout 2
idex: wbout 0, mout 8, exout 2, pcout 000e, rd1out 0001, rd2out 0001, sextout fff8, instaout 1 instbout 1 instcout 7 idexout 5
ifid: pcout 0010, irout 0000
newpc: 0012
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 1, readdataout xxxx, aluresultout 0003
exmem: wbout 0, mout 8, pcaddout fffe, zeroout 1, overout 0, aluresout 0000, rd2out 0001, wdout 1 rtout 1
idex: wbout 1, mout 0, exout 5, pcout 0010, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0012, irout 0000
newpc: 0014
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

WRITE: 0003 to register 7
     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0003

memwb: wb 0, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout 0010, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 0012, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0014, irout 0000
newpc: 0016
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0003

memwb: wb 1, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout 0012, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 0014, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0016, irout 0000
newpc: 0018
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0003

newpc: 001a

Get here on misc, user is 0, reason is 9
Exiting VeriWell for SPARC at time 4260
0 Errors, 0 Warnings, Memory Used: 4399945
Compile time = 0.4, Load time = 4.8, Simulation time = 4.4

Normal exit
Thank you for using VeriWell for SPARC
