VeriWell for SPARC HDL     <Version 2.0.3b>    Sun Nov 24 10:29:21 1996

  This is a free version of the VeriWell for SPARC Simulator
  Distribute this freely; call 1-800-VERIWELL for ordering information
  See the file "!readme.1st" for more information

  Copyright (c) 1994 Wellspring Solutions, Inc.
            All rights reserved

Entering Phase I...
Compiling source file : pipealu.v
The size of this model is [85%, 68%] of the capacity of the free version

Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
   exercise
   oai21
   oi332
   ai332
   one

FREEZE cleared
UPCLOCK
     reg: $0:0000 $1:0001 $2:7fff $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 0, readdataout xxxx, aluresultout 0000
exmem: wbout 0, mout 0, pcaddout 0000, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout fffe, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0000, irout 0532
newpc: 0002
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:7fff $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 0, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout fffe, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 0000, rd1out 0001, rd2out 7fff, sextout 0032, instaout 1 instbout 2 instcout 3 idexout 0
ifid: pcout 0002, irout 0000
newpc: 0004
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:7fff $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 1, readdataout xxxx, aluresultout 0000
exmem: wbout 1, mout 0, pcaddout 0064, zeroout 0, overout 1, aluresout 8000, rd2out 7fff, wdout 3 rtout 2
idex: wbout 1, mout 0, exout 5, pcout 0002, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0004, irout 0000
newpc: 0006
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:7fff $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

memwb: wb 1, readdataout xxxx, aluresultout 8000
exmem: wbout 1, mout 0, pcaddout 0002, zeroout 1, overout 0, aluresout 0000, rd2out 0000, wdout 0 rtout 0
idex: wbout 1, mout 0, exout 5, pcout 0004, rd1out 0000, rd2out 0000, sextout 0000, instaout 0 instbout 0 instcout 0 idexout 0
ifid: pcout 0006, irout 0000
newpc: 0008
UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

WRITE: 8000 to register 3
     reg: $0:0000 $1:0001 $2:7fff $3:8000 $4:0004 $5:0005 $6:0006 $7:0007

newpc: 000a

Get here on misc, user is 0, reason is 9
Exiting VeriWell for SPARC at time 3540
0 Errors, 0 Warnings, Memory Used: 4399945
Compile time = 0.4, Load time = 4.8, Simulation time = 3.1

Normal exit
Thank you for using VeriWell for SPARC
