VeriWell for SPARC HDL     <Version 2.0.3b>    Wed Nov 13 02:28:22 1996

  This is a free version of the VeriWell for SPARC Simulator
  Distribute this freely; call 1-800-VERIWELL for ordering information
  See the file "!readme.1st" for more information

  Copyright (c) 1994 Wellspring Solutions, Inc.
            All rights reserved

Entering Phase I...
Compiling source file : datapath.v
The size of this model is [54%, 40%] of the capacity of the free version

Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
   exercise
   oai21
   oi332
   ai332
   one

UPCLOCK
(00) dmem: 00 00 00 02 00 04 00 06
(08) dmem: 00 08 00 0a 00 0c 00 0e
(10) dmem: 00 10 00 12 00 14 00 16
(18) dmem: 00 18 00 1a 00 1c 00 1e

     reg: $0:0000 $1:0001 $2:0002 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

      pc: 0000 ir: 0427

regdst   1
alusrc   0
memtoreg 0
regwrite 1
memread  0
memwrite 0
branch   0
aluop    10
alucon   111
aluresult: 0000
UPCLOCK
WRITE: 0000 to register 2
     reg: $0:0000 $1:0001 $2:0000 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

      pc: 0002 ir: 8501

regdst   0
alusrc   0
memtoreg 0
regwrite 0
memread  0
memwrite 0
branch   1
aluop    01
alucon   110
aluresult: 0001
UPCLOCK
     reg: $0:0000 $1:0001 $2:0000 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

      pc: 0004 ir: 0720

regdst   1
alusrc   0
memtoreg 0
regwrite 1
memread  0
memwrite 0
branch   0
aluop    10
alucon   000
aluresult: 0000
UPCLOCK
WRITE: 0000 to register 2
     reg: $0:0000 $1:0001 $2:0000 $3:0003 $4:0004 $5:0005 $6:0006 $7:0007

      pc: 0006 ir: 0741

regdst   1
alusrc   0
memtoreg 0
regwrite 1
memread  0
memwrite 0
branch   0
aluop    10
alucon   001
aluresult: 0007
UPCLOCK
WRITE: 0007 to register 4
     reg: $0:0000 $1:0001 $2:0000 $3:0003 $4:0007 $5:0005 $6:0006 $7:0007

      pc: 0008 ir: 0a62

regdst   1
alusrc   0
memtoreg 0
regwrite 1
memread  0
memwrite 0
branch   0
aluop    10
alucon   010
aluresult: 0007
UPCLOCK
WRITE: 0007 to register 6
     reg: $0:0000 $1:0001 $2:0000 $3:0003 $4:0007 $5:0005 $6:0007 $7:0007

      pc: 000a ir: 0a62

regdst   1
alusrc   0
memtoreg 0
regwrite 1
memread  0
memwrite 0
branch   0
aluop    10
alucon   010
aluresult: 0007
UPCLOCK
WRITE: 0007 to register 6
     reg: $0:0000 $1:0001 $2:0000 $3:0003 $4:0007 $5:0005 $6:0007 $7:0007

      pc: 000c ir: 0000

regdst   1
alusrc   0
memtoreg 0
regwrite 1
memread  0
memwrite 0
branch   0
aluop    10
alucon   000
aluresult: 0000

Get here on misc, user is 0, reason is 9
Exiting VeriWell for SPARC at time 16000
0 Errors, 0 Warnings, Memory Used: 3537674
Compile time = 0.3, Load time = 3.8, Simulation time = 4.2

Normal exit
Thank you for using VeriWell for SPARC
