Amiga Advanced Graphics Architecture (AGA) documentation.
Genetic's HTML version 1.1b


  1. Summary of new features for AGA
  2. Explanation of the new features
  3. List of registers sorted by address
  4. List of registers sorted alphabetically
  5. New Lisa display and sprite modes



Back 2 Main-index.
Some coding stuff. MC680x0 Assembler coding links. Info about our productions. Genetic-homepage.

"Some credits."

Originally typed by Fireflash and Sponge of Combat 18     		(24.08.93)
Amigaguided and Page 19 added by Schwartzenegger of TFA   		(29.09.93)
Finalised (more links, endnode bug sorted) by Kyzer/CSG   		(22.05.96)
More finalised (changed to HTML and put on the net) by Solo/Genetic	(01-11-96)

History HTML version:

1.0	(1-nov-1996)
	- straight port from amiga guide 2 HTML.
1.1	(2-nov-1996)
	- fixed a lot of links.
	- put in 3 files i.s.o. 1 for faster access.
	  and the aga.html file was 2 long for netscape (160 kb) dono why..
1.1b	(3-Nov-1996)
	- created some tables.


Todo:
	- still have to fix some links.
	- make some cool tables ipv. the ascii 1's.


Index.

"Summary of new features for AGA"

  1. 32 bit wide data bus supports input of 32-bit wide bitplane data and allows doubling of memory bandwidth. Additional doubling of bandwidth can be achieved by using fast page mode RAM. The same bandwidth enhancements are available for sprites. Also the maximum number of bitplanes usable in all modes was increased to eight (8).
  2. The colour palette has been expanded to 256 colours deep and 25 bits wide (8 RED, 8 GREEN, 8 BLUE, 1 GENLOCK). This permits display of 256 simultaneous colours in all resolutions. A palette of 16777216 colours are available in all resolutions.
  3. 28Mhz clock input allows for cleaner definition of HIRES and SHRES pixels ALICE`S clock genarator is synchronized by means of LISA`s 14MHz and SCLK outputs, Genlock XCLK and XCLKEN pins have been eliminated (external MUX is now required).
  4. A new register bit allows sprites to appear in the screen border regions (BRDRSPRT - See BPLCON3).
  5. A bitplane mask field of 8 bits allows an address offset into the colour palette.
  6. Two 4-bit mask fields do the same for odd and even sprites.
  7. In Dual Playfield modes, 2 4-bitplane playfields are now possible in all resolutions.
  8. Two Extra high-order playfield scrollbits allow seamless scrolling of up to 64 bit wide bitplanes in all resolutions. Resolution of bitplane scroll, display window,and horizontal sprite position has been improved to 35ns in all resolutions.
  9. A new 8-bitplane HAM mode has been created, 6 for colours and 2 for control bits. All HAM modes are available in all resolutions (not just LORES as before).
  10. A RST_input pin has been added, which resets all the bits contained in registers that were new for ECS or LISA: BPLTCON3, BPLCON4, CLXCON2, , FMODE.
  11. Sprite resolution can be set to LORES,HIRES,SHRES,independant of bitplane resolution.
  12. Attached Sprites are now available in all resolutions.
  13. Hardware Scan Doubling support has been added for bitplanes and sprites. This is intended to allow 15KHz screens to be intelligently displayed on a 31KHz monitor and share the display with 31KHz screens.

Index.

"Explanation of the new features"


BITPLANES
There are now 8 bitplanes instead of 6. In single playfield modes they can address 256 colours instead of 64. As long as the memory architecture can support the bandwidth, all 8 bitplanes are available in all 3 resolutions In the same vein, 4+4 bitplane dualplayfield is available in all 3 resolutions, unless bitplane scan-doubling is enabled, in which case both playfields share the same bitplane modulus register. Bits 15 thru 8 of
BPLCON4 comprise an 8 bit mask for the 8 bitplane address, XOR`ing the individual bits. This allows the copper to exchange colour maps with a single instruction.

BPLCON1 now contains an 8 bit scroll value for each of the playfields. Granularity of scroll now extends down to 35nSec.(1 SHRES pixel), and scroll can delay playfield thru 32 bus cycles. Bits BPAGEM and BPL32 in new register FMODE control size of bitplane data in BPLxDAT thru BPLxDAT.

The old 6 bitplane HAM mode, unlike before, works in HIRES and SHRES resolutions.

As before bitplanes 5 and 6 control it`s function as follows:

    BP6BP5REDGREENBLUE
    00select new base reg.(1-16)
    01holdholdmodify
    10modifyholdhold
    11holdmodifyhold

There is a new 8 bitplane HAM (Hold and Modify) mode. This mode is invoked when BPU field in BPLCON0 is set to 8 , and HAMEN is set. Bitplanes 1 and 2 are used as control bits analagous to the function of bitplanes 5 and 6 in 6 bitplane HAM mode:

    BP2BP1REDGREENBLUE
    01select new base reg.(1-64)
    01holdholdmodify
    10modifyholdhold
    11holdmodifyhold

Since only 6 bitplanes are available for modify data, the data is placed in 6 MSB. The 2 LSB are left unmodified, which allows creation of all 16,777,216 colours simultaneously, assuming one had a large enough screen and picked one`s base registers judiciously. This HAM mode also works in HIRES and SHRES modes.

For compatibility reasons EHB mode remains intact. Its existence is rather moot in that we have more than enough colours in the colour table to replace its functionality. As before, EHB is invoked whenever SHRES = HIRES = HAMEN= DPF = 0 and BPU = 6. Please note that starting with ECS DENISE there is a bit in BPLCON2 which disables this mode (KILLEHB).

Bits PF2OF2,1,0 in BPLCON3 determine second playfield`s offset into the colour table. This is now necessary since playfields in DPF mode can have up to 4 bitplanes. Offset value are as defined in register map.

BSCAN2 bit in FMODE enables bitplane scan-doubling. When V0 bit of DIWSTRT matches V0 of vertical beam counter, BPL1MOD contains the modulus for the display line, else BPL2MOD is used. When scan-doubled both odd and even bitplanes use the same modulus on a given line, whereas in normal mode odd bitplanes used BPL1MOD and even bitplanes used BPL2MOD. As a result Dual Playfields screens will probably not display correctly when scan-doubled.

SPRITES

Bits SPAGEM and SPR32 in FMODE whether size of sprite load datain SPRxDAT thru SPRxDAT is 16,32, or 64 bits, analagous to bitplanes. BPLCON3 contains several bits relating to sprite behavior. SPRES1 and SPRES0 control sprite resolution, whether they conform to theECS standard or override tp LORES,HIRES,or SHRES. BRDRSPRT, when high,allows sprites to be visible in border areas. ESPRM7 thru ESPRM4 allow relocation of the even sprite colour map. OSPRM7 thru OSPRN4 allow relocation of the odd sprite colour map. In the case of attached sprites OSPRM bits are used.

SSCAN2 bit in FMODE enables sprite scan-doubling. When enabled, individual SH10 bits in SPRxPOS registers control whether or not a given sprite is to be scan-doubled. When V0 bit of SPRxPOS register matches V0 bit of vertical beam counter, the given sprite`s DMA is allowed to proceed as before. If the don`t match, then sprite DMA is disabled and LISA reuses the sprite data from the previous line. When sprites are scan-doubled, only the position and control registers need be modified by the programmer; the data registers need no modification.

NOTE: Sprite vertical start and stop positions must be of the same parity, i.e. both odd or even.

COMPATIBILITY

RST_pin resets all bits in all registers new to AA. These registers include: BPLCON3, BPLCON4, CLXCON2, DIWHIGH, FMODE. ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in BPLCON3 that are never accessed by old copper lists, and in addition are required by old style copper lists to be in their default settings.Specifically ECSENA forces the following bits to their default low settings: BRDRBLNK, BRDNTRAN, ZDCLKEN, EXTBLKEN, and BRDRSPRT.

CLXCON2 is reset by a write to CLXCON, so that old game programs will be able to correctly detect collisions.

DIWHIGH is reset by writes to DIWSTRT or DIWSTRT. This is interlock is inhertied from ECS Denise.

GENLOCK

Lots of new genlock features were added to ECS DENISE and arecarried over to LISA. ZDBPEN in BPLCON2 allows any bitplane, selected by ZDBPSEL2,1,0,to be used as a transparency mask (ZD pin mirrors contents of selected bitplane). ZDCTEN disables the old COLORx is transparent mode, and allows the bit31 position of each colour in the colour table to control transparency.ZDCLKEN generates a 14MHz clock synchronized with the video data that can be used by video post-processors. Finally, BRDNTRAN in BPLCON3 generates an opaque border region which can be used to frame live video.

COLOUR LOOKUP TABLE

The colour table has grown from 32 13-bit registers to 256 25-bit registers. Several new register bits have been added to BPLCON3 to facilitate loading the table with only 32 register addresses. LOCT, selects either the 16 MSB or LSB for loading. Loading the MSB always loads the LSB as well for compatibility, so when 24 bit colours are desired load LSB after MSB. BANK2,1,0 of 8 32 address banks for loading as follows:

    BANK2BANK1BANK0Color address range
    000COLOR00 - COLOR1F
    001COLOR20 - COLOR3F
    010COLOR40 - COLOR5F
    011COLOR60 - COLOR7F
    100COLOR80 - COLOR9F
    101COLORA0 - COLORBF
    110COLORC0 - COLORDF
    111COLORE0 - COLORFF
RDRAM bit in BPLCON2 causes LISA to interpret all colour table accesses as reads. Note: There is no longer any need to "scramble" SHRES colour table entries. This artifice is no longer required and pepole who bypass ECS graphics library calls to do their own 28MHz graphics are to be pointed at and publicly humiliated.

COLLISION

A new register CLXCON2 contains 4 new bits. ENBP7 and ENBP6 are the enable bits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MPBP8 are their match value bits. CLXDAT is unchanged.

HORIZONTAL COMPARATORS

All programmable comparators with the exception of VHPOSW have 35nSec resolution.: DIWHIGH, HBSTOP, SPRCTL, BPLCON1. BPLCON1 has additional high-order bits as well. Note that horizontal bit position representing 140nSec resolution has been changed to 3rd least significant bit,where before it used to be a field`s LSB, For example, bit 00 in BPLCON1 used to be named PF1H0 and now it`s called PF1H2.

COERCION OF 15KHZ TO 31KHZ

We have added new hardware features to LISA to aid in properly displaying 15KHz and 31KHz viewports together on the same 31KHz display. LISA can globally set sprite resolution to LORES, HIRES, or SHRES. LISA will ignore SH10 compare bits in SPRxPOS when scan-doubling, thereby allowing ALICE to use these bits individually set scan-doubling.
Index.


"New Lisa display and sprite modes"

        We now have a palette of 2~24 colours.

        LORES  (320x200)
        ----------------

        6 Bitplane (non HAM, non EHB)   64 colours                      !
        7 Bitplane                      128 colours                     !
        8 Bitplane                      256 colours                     !
        8 Bitplane HAM                  Any 2^24 colours                !

        Dual playfield, Max 4 bitplane per playfield. 16 colours        !
        per playfield. The bank of 16 colours in the 256 colour palette
        is selectable per playfield.

        HIRES  (640x200)
        ----------------

        5 Bitplanes             32 colours                              @
        6 Bitplanes             64 colours                              @
        7 Bitplanes             128 colours                             @
        8 Bitplanes             256 colours                             @
        6 Bitplanes EHB         32 * 2 colours                          @
        6 Bitplanes HAM         4096 colours                            @
        8 Bitplanes HAM         any of 2^24 colours                     @

        Dual playfield, max 4 bitplane per playfield 16 colours per     ! or @
        playfield. The bank of 16 colours in the 256 colour palette
        is selectable per playfield.

        SUPERHIRES (1280X200)
        ---------------------

        1 or 2 bitplanes, as ECS, but no color fudging                  !
        3 Bitplanes             8 colours				@
        4 Bitplanes             16 colours				@
        5 Bitplanes             32 colours				$
        6 Bitplanes             64 colours				$
        7 Bitplanes             128 colours				$
        8 Bitplanes             256 colours				$
        6 Bitplanes EHB         32 * 2 colours				$
        6 Bitplanes HAM         4O96 colours				$
        8 Bitplanes HAM         any of 2~24 colours			$

        Dual Playfield, max 4 bitplanes per playfield			@ or $
        16 colours per playfield. The bank of 16 of colours
        in the 256 colours palette is selectable per playfield.

        VGA  (640X480 non-interlaced)
        -----------------------------


        1 or 2 bitplanes, as ECS, but no colour fudging			!
        3 Bitplanes		8 colours				@
        4 Bitplanes		16 colours				@
        5 Bitplanes		32 colours				$
        6 Bitplanes		64 colours				$
        7 Bitplanes		128 colours				$
        8 Bitplanes		256 colours				$
        6 Bitplanes EHB         32 * 2 colours				$
        6 Bitplanes HAM         4O96 colours				$
        8 Bitplanes HAM         any of 2~24 colours			$

        Dual playfield,Max 4 bitplanes per playfield                    @ or $
        16 colours per playfield . The bank of 16 colours
        in the 256 colour palette is selectable per playfield


        Super 72 (848x614 interlaced, 70 Hz frame rate)
        -----------------------------------------------


        1 or 2 bitplanes, as ECS, but no colour fudging         	1X
        3 Bitplanes                     8 colours               	2X
        4 Bitplanes                     16 colours              	2X
        5 Bitplanes                     32 colours              	4X
        6 Bitplanes                     64 colours              	4X
        7 Bitplanes                     128 colours             	4X
        8 Bitplanes                     256 colours             	4X
        6 Bitplanes EHB                 32 * 2 colours          	4X
        6 Bitplanes HAM                 4O96 colours            	4X
        8 Bitplanes HAM                 any of 2~24 colours     	4X

        Dual playfield,Max 4 bitplanes per playfield            	2X or 4X
        16 colours per playfield . The bank of 16 colours
        in the 256 colour palette is selectable per playfield


        All playfield scrolling is now in 35ns increments.
        Pre AA scrolling was in 140ns increments.

Scroll Range as Programmed in BPLCON1
-----------------------------------


    1x ModeLOWRES PixelsSHRES Pixels
    LOWRES0-150-63
    HIRES 0-70-31
    SHRES 0-30-15
    2x ModeLOWRES PixelsSHRES Pixels
    LOWRES0-310-127
    HIRES 0-150-63
    SHRES 0-70-31
    4x ModeLOWRES PixelsSHRES Pixels
    LOWRES0-630-255
    HIRES 0-310-127
    SHRES 0-150-63
Sprites ------- All sprites can now be displayed in either:
  1. ECS default mode
  2. 140 ns (this is not ECS mode!)
  3. 70 ns
  4. 35 ns
on display resolution. eg 35 ns sprites on a lores screen, or 140 ns sprites on a superhires screen. Sprites are either 16, 32, or 64 bits wide. Sprites can be attatched in any mode (formerly could not attach sprites in the ECS SHRES 35ns resolution mode). Can use any bank of 16 colours from the 256 colour palette for the sprite colours. Key: ! needs 1x Bandwidth (old modes) @ needs 2x Bandwidth (normal CAS 32bit bus with or double CAS 16 bit bus width) $ needs 4x Bandwidth (double CAS 32bit bus width)
Index. counter