Ref: 03250428 Title: IB/3 Firmware, Configuration, and Jumper Settings Date: 12/14/87 Copyright 3Com Corporation, 1991. All rights reserved. The following reviews IB/3 firmware levels, jumper settings, and other configuration details. To enter into config, type fc at the prompt with a 9600 baud terminal attached to the console port. If the disk is write protected and the MCPU-20 firmware configuration shows the Initial boot source is Auto, the terminal should display an error message to the effect that the disk is write If the disk is 48 TPI, the console port terminal should report read or seek errors when operating an IB/3 with a MCPU-20. If a regular MCPU is used, the disk drive and disk should be 48 TPI. Firmware Levels The release memo for IB/3 and SW/20-IB Version 10000 (preliminary dated Nov. 19th) shows the correct firmware: ITCM - none SIO - M1SYNC Rev.01D or later MCPU/20 - M3MMON Rev.0D or later M1EC2B Rev.01A or later Clock Jumper Settings Clock jumpers should be set to external when operating with a CSU/ DSU; internal on one board and external on the board at the opposite end of the link. If the ITC/M board is Rev.0A, the clock jumpers are as follows: Jumper settings for prototype rev. 0A ITCM boards. E77 E57 E78 INTERNAL o o o o o o l l o-o o o o o l l l l o o o o o o EXTERNAL o-o o o o o o o o o o o l l l l o o o o o o where, a "-" or "l" denotes connected and "o" is the berg-stick pin. The released IB Installation and Operation Guide (09-0107-00), is incorrect. The Software and Hardware Release Memo, shows the jumpering of Rev.00 ITC/M boards as follows: Configuration area E77 shorting plug effects: 1-2 Transmit clock derived from send timing clock supplied by CSU/DSU or attatched modem. 3-4 Transmit clock derived from onboard oscillator 5-6 Transmit clock derived from receive timing clock supplied by CSU/DSU or attatched modem. Board number and Multibus interrupt jumpers: E65 Pins Interrupt E66 Pins Connected ITC/M Number 1-2 3-4 Level 1-2 3-4 5-6 7-8 Slot 1 (4th ITC/M) In In 4 Out Out Out In H 2 (3rd ITC/M) Out In 5 Out Out In Out G 3 (2nd ITC/M) In Out 6 Out In Out Out F 4 (1st ITC/M) Out Out 7 In Out Out Out E Slots are designated as being A thru H; the IEC/M is in slot A or B, the MCPU in slot C, and slot D does not have MBI connectors. The ITC/M number is read by the MCPU20 after power-on or reset. Multibus base address, configuration area 67 for Systems with 1 or 2 ITC/M Boards: Base Address Slot Pins Connected (in hex) 1-2 3-4 5-6 1st ITC/M A0000 E Out In Out 2nd ITC/M 80000 F Out In In For Systems with 3 or 4 ITC/M Boards: Base Address Slot Pins Connected (in hex) 1-2 3-4 5-6 1st ITC/M E0000 E Out Out Out 2nd ITC/M C0000 F Out Out In 3rd ITC/M A0000 G Out In Out 4th ITC/M 80000 H Out In In ITC/M boards are inserted in the chassis with positions reversed from those of SIO's (eg. ITC/M #1 inserted where the 4th SIO would be, ITC/M #2 inserted where the 3rd SIO would be. Configuration Area E80: Connect pins 3-5 and 4-6 for 500 Kbps operation and higher. Connect pins 1-3 and 2-4 for 100-500 Kbps operation. Configuration Areas E82 and E83: Connect pins 1-3 and 2-4 to enable the ITC/M board to run self-test without a modem or CSU/DSU attatched. These loopback the clocks (TXC and RXC).