Ref: 03250416 Title: CS/200B Trouble-Shooting Aids and Self Tests Date: 2/25/88 Copyright 3Com Corporation, 1991. All rights reserved. For those of you who would like knowledge of the self-tests performed on the CS/200, here they are. All of this info may change with the CS/210 (floppy based). INDEX TO TESTS A) CPU LEVEL 1 TESTS 1) OTL Timer Reset Test 2) Prom Low Byte Checksum Test 3) Prom High Byte Checksum Test 4) EEPROM Initialization Test 5) UART Data Bus Ripple Test 6-8) 8253 3 Channel Counter Tests 9) RAM Data Bus Ripple Test a) RAM Address Bus Ripple Test b) RAM March Test c) RAM Refresh Test d) 8253 Interrupt Test B) SIO SECTION CONFIDENCE TESTS 1) Serial Controller Polled Tests (test #'s 1-a) 2) Serial Controller rx-tx interrupts (test #'s b-14) C) ETHERNET CONTROLLER CONFIDENCE TESTS 1) LANCE Initialization Test 2) LANCE Transmission Test 3) LANCE Transmission and Reception Test 4) LANCE Trans. and Recept. w/ odd length Test 5) LANCE Trans. and Recept. w/o CRC Error Test 6) LANCE Trans. and Recept. w/ CRC Error Test The following describes the methodology used in Prom-based Confidence Tests (Self-Test): A) CPU LEVEL 1 TESTS Self-Test: A CS/200 may fail self-test in one of two ways; it may display a failure message on the monitor such as: Series 200 Power-up CPU - Passed C1 MMON rev.01 EC - Passed Station Address - 08000200FFFF SIO - Failed Test # 0D or it may not be able to display the failure message as it may not have programmed the UARTs yet or for some other reason. In those cases where no message is displayed, the onboard LEDs, CR10 - CR16, may be used to decode the failure. CR10 and CR11 are decoded for Section number, and CR12 - CR16 are decoded for the Test number within that section (CR16 is the least signifi-cant bit.) When using a Tektronics 1240 with a PM203 and 68000 Mneumonics ROM Pack, failures are declared by a MOVEQ to D3 (Software Format.) CPU Level 1 Tests (MPTests) - Section 0 1) OTL Timer Reset - the OTL timer and a software counter are enabled at the same time. The board must be reset by the OTL timer circuitry before the software counter expires. This test checks the reset and init circuitry and also uses the CAS.PAL (U21) and U36 on schematic page 16. 2) PROM Low Byte Checksum - Odd addresses in EPROM (000001- 01ffff) are read by the 68000 and manipulated internally by the 68000. (The 68000 reads the lower byte of odd addresses) The result of the 68000 calculations is compared against the stored checksum. 3) PROM High Byte Checksum - Even addresses in EPROM is accessed and the upper byte read by the 68000. The same data validation method used as in Low Byte Checksum. Tests 2 and 3 should validate the data programmed into U39 and U38 respectively, the address and data busses, and output enable circuitry between the 68000 and EPROMs. If either of these tests fail and the data obtained from EPROM is the same as obtained on a known good board, the 68000 is probably at fault. 4) EEPROM Initialization - The first time the CS/200 is powered-up, as the values in EEPROM may be random, the EEPROM is programmed with various parameters. The address E00001 is read to determine if the EEPROM has been initialized. If the data pattern 5A is read the EEPROM has been previously initialized and will not be re-initialized so as not to change parameters set to other than default values by the user. The ability to select EEPROM is checked, and some level of confidence in the ability to perform a read from EEPROM may be established. 5) UART Data Bus Ripple - The UART at U85 is used. The WR13 register is used , the 68000 executing successive writes and reads, starting with a data pattern of all 0's, ripples a 1 accross the data bus verifying each write with a following read. WR13 is selected by writing 0D to addr 800003 before each access. This test verifies the data bus to this UART only, data bus integrity to the other UARTs will be tested in subsequent tests when the UARTS are asked to perform various SIO tests. UARTS are all initialized at the end of test 5 and programmed with base interrupt vectors, the number of Ports present is sensed and ports are configured to parameters in EEPROM. Port 0 is reconfigured if not selected to be a monitor port and if another port is selected to be the monitor port it will be configured as such at this time. 6-8) 8253 Timer Test - by loading all three counters with an initial value, arming them, and later saving each counter and reading their hold registers verifies the integrity of the control cir-cuitry, address and data busses to the 8253 Timer (U67). Result of each counter countdown must be < 55FF and > 5500 when saved. 9) RAM Data Bus Ripple - Using address 100000 (the lowest address in RAM) as a test location ripples a 1 in a field of 0's across the data bus. Basic data path integrity is checked to RAM. a) RAM Address Bus Ripple - verifies that all address and data lines to RAM have no opens and are not shorted by writing 55(hex) from location 100000 to 17FFFF to each address generated by rippling a 1 in a field of 0's. As each location is verified its contents will be changed to AA and reverified. b) RAM March Test - Verifies that all locations in RAM can be read and written to, by writing 5555(hex) to every location in RAM and starting at addr. 100000 verifies each location and writes AAAA to it upon reading the correct data pattern (5555). When the end of RAM (addr 17FFFF) is reached, AAAA is verified and re-written 5555 starting at the end of RAM. When 100000 is reached, the procedure is repeated with an initial test pattern of AAAA. A single bit failure during this test will usually be the RAM device supplying that bit; a multi-bit failure may be caused by refresh collisions or intermittent addressing and/or data lines and buffers, or will be a timing/cycle problem. c) RAM Refresh Test - All RAM is initialized with each locations' address used as its data pattern. After approximately 1.5 seconds without any RAM activity the data is compared to its location. A failure of this test will usually be a refresh problem, unless it is a single bit problem which reoccurs, in which case the RAM device or data path for that bit may still have problems. The board may function for as long as 15 minutes with the Refresh PAL removed and will pass self-test. d) Timer Generated Interrupt - Timer channel 2 of the 8253 is programmed to produce an interrupt after approx. 100 microseconds. The interrupt is checked for proper level and, if IPL2, will be cleared automatically. B) SIO Section Self-Tests - Section 1 1-a) Serial Controllers Polled - All UARTs are programmed for asynchronous, polled driven, 9600 baud. A group of characters is transmitted and received via the internal loopback circuitry. Receive characters are verified and each UART is checked for proper status of both channels it controls. This test checks Baud Rate generation. b-14) Serial Controllers RX-TX Interrupts - All UARTS are programmed for asynchronous, interrupt driven mode. The interrupt generation and vector (from the UART involved), status and characters received are checked for each channel. This test checks the interrupt and vector generation logic. Drivers to the RS-232 connectors are disabled during these tests and are tested fully by the software SIO Loopback tests run during System Verification. C) Ethernet Controller Self-Tests - Section 2 1) LANCE Initialization Test - U66 (the LANCE) is reset and programmed with the transmitter and receiver disabled. Number of LANCE interrupts (should be 1) to the CPU, status are checked. Most failures are caused by a bad LANCE or Lance Data Path problems, although lance addressing may be at fault also. Other common problems are no DTACK after an access to the LANCE (addr 20000X) usually as a result of LANCE Chip Select problems, and LANCE interrupt path to the 68000 problems. 2) LANCE Single Fragment Transmission - U66 is reset and programmed with the transmitter enabled and the receiver disabled. Number of IPL3 interrupts received (should be 2), LANCE status are checked as well as the ability of the LANCE to update its ring structures. 3) LANCE Single Fragment Transmission and Reception - U66 is reset and programmed with transmitter and receiver enabled. Number of IPL3's (should be 3), status and ring structure updates are checked. 4) LANCE Odd length TX and RX - U66 is reset and programmed with transmitter and receiver enabled and an odd number of bytes to be transmitted. Number of IPL3's (should be 3) status and ring structure updates are checked. 5) LANCE TX and RX without CRC - U66 is reset and programmed with transmitter and receiver and CRC checking enabled. Number of IPL3's (should be 3), status (must not show CRC error) and ring structure updates are checked. 6) LANCE TX and RX with CRC Error - U66 is reset and programmed with transmitter and receiver and CRC checking enabled. A bad CRC is appended to the packet to be transmitted. Number of IPL3's (should be 3), status (must show CRC error) and ring structure are checked. Tests 2 through 6 may be caused by a variety of problems, however, most will be caused by LANCE to RAM address or data path problems and not LANCE to 68000 problems. You will want to determine first that the LANCE (U66) if socketed is not the problem (by substitution). Next, you will want to determine why the failure was declared, whether interrupts, status, or ring structure. Most problems will be status. The SIA and associated circuitry may also cause any of these failures.