include graphics/gfx.i include powerpc_lib.i ;// XREF / XDEF ; xref _PowerPCBase xref ChunkyBuffer ; xref TempBuffer xref HiddenBitmap xref AreaHeight xref AreaWidth xdef ChunkyToPlanar_PPC xdef ChunkyToPlanar_PPC_II ;;/ ;// Macros **** citf: Convert Integer to Floating Signed (Double Precision) * * parameters: * 1: destination FP-Register * 2: intermediate FP-Register (MUST hold the value $4330000080000000) * 3: source GP-Register citf macro xoris trash,\3,$8000 sw trash,_CITF_TEMP+4 lf \1,_CITF_TEMP fsub \1,\1,\2 endm section "Voxelspace_Calc",code cpu POWERPC smalldata smallcode setlocal 256,r13 vea ;;/ ;// ChunkyToPlanar_PPC (converts chunky data to bitplane data) merge macro and r18,\1,\3 xor \1,r18,\1 and r19,\2,\3 xor \2,r19,\2 slwi r18,r18,\4 srwi \2,\2,\4 or \1,\1,\2 or \2,r19,r18 endm ****************************************************************************** * * ChunkyToPlanar_PPC * * converts chunky data into bitplane data (using Bitmap Structure) * works ONLY with a depth of 8! * * original algorithm by James McCoull (I found the source somewhere * on the AMINET CD's) * ****************************************************************************** ChunkyToPlanar_PPC prolog 256 pushgpr r14-r28 subi local,local,32 ; space for temporary variables lw r3,HiddenBitmap ;b exit la r3,bm_Planes+32(r3) ;r11 -> after 8 plane ptrs lwzu r16,-4(r3) ;read 8 plane ptrs lwzu r15,-4(r3) lwzu r14,-4(r3) lwzu r28,-4(r3) lwzu r12,-4(r3) lwzu r11,-4(r3) lwzu r10,-4(r3) lwzu r9,-4(r3) subi r9,r9,4 ;prepare for postincrement subi r10,r10,4 subi r11,r11,4 subi r12,r12,4 subi r28,r28,4 subi r14,r14,4 subi r15,r15,4 subi r16,r16,4 lw r3,ChunkyBuffer ; r3 = chunky buffer ; r9-r16 = output area lh r5,AreaHeight lh r21,AreaWidth mullw r5,r5,r21 add r4,r3,r5 ;r4 -> end of chunky data liw r5,$00ff00ff ;load mask values liw r6,$0f0f0f0f liw r7,$33333333 liw r8,$55555555 first_case lwz r21,0(r3) lwz r23,4(r3) lwz r20,8(r3) lwz r22,12(r3) lwz r24,2(r3) lwz r25,10(r3) lwz r26,6(r3) lwz r27,14(r3) lhz r17,16(r3) mh r21,r17 lhz r17,24(r3) mh r20,r17 lhz r17,20(r3) mh r23,r17 lhz r17,28(r3) mh r22,r17 lhz r17,18(r3) mh r24,r17 lhz r17,26(r3) mh r25,r17 lhz r17,22(r3) mh r26,r17 lhz r17,30(r3) mh r27,r17 addi r3,r3,32 merge r21,r20,r5,8 ;now convert it merge r23,r22,r5,8 merge r21,r23,r6,4 merge r20,r22,r6,4 merge r24,r25,r5,8 merge r26,r27,r5,8 merge r24,r26,r6,4 merge r25,r27,r6,4 merge r23,r26,r7,2 merge r22,r27,r7,2 merge r23,r22,r8,1 merge r26,r27,r8,1 merge r21,r24,r7,2 merge r20,r25,r7,2 merge r21,r20,r8,1 merge r24,r25,r8,1 stw r27,0*4(local) ;plane 0 stw r26,1*4(local) ;plane 1 stw r22,2*4(local) ;plane 2 stw r23,3*4(local) ;plane 3 stw r25,4*4(local) ;plane 4 stw r24,5*4(local) ;plane 5 stw r20,6*4(local) ;plane 6 stw r21,7*4(local) ;plane 7 cmpw r4,r3 beq final_case main_case lwz r21,0(r3) lwz r23,4(r3) lwz r20,8(r3) lwz r22,12(r3) lwz r24,2(r3) lwz r25,10(r3) lwz r26,6(r3) lwz r27,14(r3) lhz r17,16(r3) mh r21,r17 lhz r17,24(r3) mh r20,r17 lhz r17,20(r3) mh r23,r17 lhz r17,28(r3) mh r22,r17 lhz r17,18(r3) mh r24,r17 lhz r17,26(r3) mh r25,r17 lhz r17,22(r3) mh r26,r17 lhz r17,30(r3) mh r27,r17 addi r3,r3,32 lwz r17,0*4(local) stwu r17,4(r9) merge r21,r20,r5,8 merge r23,r22,r5,8 lwz r17,1*4(local) stwu r17,4(r10) merge r21,r23,r6,4 merge r20,r22,r6,4 lwz r17,2*4(local) stwu r17,4(r11) merge r24,r25,r5,8 merge r26,r27,r5,8 lwz r17,3*4(local) stwu r17,4(r12) merge r24,r26,r6,4 merge r25,r27,r6,4 lwz r17,4*4(local) stwu r17,4(r28) merge r23,r26,r7,2 merge r22,r27,r7,2 lwz r17,5*4(local) stwu r17,4(r14) merge r23,r22,r8,1 merge r26,r27,r8,1 lwz r17,6*4(local) stwu r17,4(r15) merge r21,r24,r7,2 merge r20,r25,r7,2 lwz r17,7*4(local) stwu r17,4(r16) merge r21,r20,r8,1 merge r24,r25,r8,1 stw r27,0*4(local) ;plane 0 stw r26,1*4(local) ;plane 1 stw r22,2*4(local) ;plane 2 stw r23,3*4(local) ;plane 3 stw r25,4*4(local) ;plane 4 stw r24,5*4(local) ;plane 5 stw r20,6*4(local) ;plane 6 stw r21,7*4(local) ;plane 7 cmpw r4,r3 bne main_case final_case lwz r17,0*4(local) stwu r17,4(r9) lwz r17,1*4(local) stwu r17,4(r10) lwz r17,2*4(local) stwu r17,4(r11) lwz r17,3*4(local) stwu r17,4(r12) lwz r17,4*4(local) stwu r17,4(r28) lwz r17,5*4(local) stwu r17,4(r14) lwz r17,6*4(local) stwu r17,4(r15) lwz r17,7*4(local) stwu r17,4(r16) exit addi local,local,32 popgpr epilog ;;/ ******************************************************************************** ;The following c2p i`m working on !!!!!! ;still it crash .... ;it is coded for PowerUP and SAS/PPC ;############################################################################## ;# macros - written by Jacek Cybularczyk (NOE/Venus Art) ;############################################################################## ;# MERGE_nBITS ;# data1, data2, temp, mask, shift ;# \1 \2 \3 \4 \5 macro MERGE_nBITS srwi \3,\2,\5 xor \3,\3,\1 and \3,\3,\4 xor \1,\1,\3 slwi \3,\3,\5 xor \2,\2,\3 endm ;############################################################################## ;# MERGE_nBITS2 ;# data1, data2, temp12, data3, data4, temp34, mask, shift ;# \1 \2 \3 \4 \5 \6 \7 \8 macro MERGE_nBITS2 srwi \3,\2,\8 srwi \6,\5,\8 xor \3,\3,\1 xor \6,\6,\4 and \3,\3,\7 and \6,\6,\7 xor \1,\1,\3 xor \4,\4,\6 slwi \3,\3,\8 slwi \6,\6,\8 xor \2,\2,\3 xor \5,\5,\6 endm ;############################################################################## ;# MERGE_8BITS ;# data1, data2, temp ;# \1 \2 \3 macro MERGE_8BITS mr \3,\1 rlwimi \1,\2,24,8,15 rlwimi \1,\2,24,24,31 rlwimi \2,\3,8,0,7 rlwimi \2,\3,8,16,23 endm ;############################################################################## ;# MERGE_8BITS2 ;# data1, data2, temp12, data3, data4, temp34 ;# \1 \2 \3 \4 \5 \6 macro MERGE_8BITS2 mr \3,\1 mr \6,\4 rlwimi \1,\2,24,8,15 rlwimi \4,\5,24,8,15 rlwimi \1,\2,24,24,31 rlwimi \4,\5,24,24,31 rlwimi \2,\3,8,0,7 rlwimi \5,\6,8,0,7 rlwimi \2,\3,8,16,23 rlwimi \5,\6,8,16,23 endm ;############################################################################## ;# MERGE_16BITS ;# data1, data2, temp ;# \1 \2 \3 macro MERGE_16BITS mr \3,\1 rlwimi \1,\2,16,16,31 rlwimi \2,\3,16,0,15 endm ;############################################################################## ;# MERGE_16BITS2 ;# data1, data2, temp12, data3, data4, temp34 ;# \1 \2 \3 \4 \5 \6 macro MERGE_16BITS2 mr \3,\1 mr \6,\4 rlwimi \1,\2,16,16,31 rlwimi \4,\5,16,16,31 rlwimi \2,\3,16,0,15 rlwimi \5,\6,16,0,15 endm ;# 8bit c2p converter. ;# written by Jacek Cybularczyk (aka Noe / Venus Art) ; .include macros.i ;############################################################################## ;# C2P converter for non-interleaved planes ;# Optimized for two Integer Units (like in MPC604) ;# ;# IN: ;# r3 pointer to chunky buffer (allocated on 32-byte boundary for better performance) ;# r4 pointer to table of plane pointers (planes[8]) ;# r5 width (aligned to 64 pixels) ;# r6 height ;# OUT: ;# none ; .extern _C2P_NI ; .extern C2P_NI ; .align 4 ChunkyToPlanar_PPC_II ;_C2P_NI ;C2P_NI: prolog 256 pushgpr r14-r31 lw r4,HiddenBitmap la r4,bm_Planes(r4) lw r3,ChunkyBuffer liw r5,320 liw r6,200 ; subi r1,r1,(32-10)*4 ; stw r2,0(r1) ; stmw r11,4(r1) srwi r5,r5,6 mullw r31,r5,r6 mtctr r31 plane0 equr r4 plane1 equr r5 plane2 equr r6 plane3 equr r7 plane4 equr r8 plane5 equr r9 plane6 equr r10 plane7 equr r31 lwz plane7,28(r4) subi plane7,plane7,4 lwz plane6,24(r4) subi plane6,plane6,4 lwz plane5,20(r4) subi plane5,plane5,4 lwz plane4,16(r4) subi plane4,plane4,4 lwz plane3,12(r4) subi plane3,plane3,4 lwz plane2,8(r4) subi plane2,plane2,4 lwz plane1,4(r4) subi plane1,plane1,4 lwz plane0,0(r4) subi plane0,plane0,4 src equr r3 temp0 equr r30 temp1 equr r29 ;dcbt 0,src ;# pre-fill cache line mask1 equr r28 mask2 equr r27 mask4 equr r26 addis mask1,0,$5555 ori mask1,mask1,$5555 addis mask2,0,$3333 ori mask2,mask2,$3333 addis mask4,0,$0f0f ori mask4,mask4,$0f0f reg00 equr r25 reg01 equr r24 reg02 equr r23 reg03 equr r22 reg04 equr r21 reg05 equr r20 reg06 equr r19 reg07 equr r18 reg10 equr r17 reg11 equr r16 reg12 equr r15 reg13 equr r14 reg14 equr r13 reg15 equr r12 reg16 equr r11 reg17 equr r2 lwz reg00,0(src) lwz reg04,4(src) lwz reg01,8(src) lwz reg05,12(src) lwz reg02,16(src) lwz reg06,20(src) lwz reg03,24(src) lwz reg07,28(src) addi src,src,32 ;dcbt 0,src # fill cache line MERGE_16BITS2 reg00,reg02,temp0,reg01,reg03,temp1 MERGE_16BITS2 reg04,reg06,temp0,reg05,reg07,temp1 lwz reg10,0(src) MERGE_8BITS2 reg00,reg01,temp0,reg02,reg03,temp1 lwz reg14,4(src) MERGE_8BITS2 reg04,reg05,temp0,reg06,reg07,temp1 lwz reg11,8(src) MERGE_nBITS2 reg00,reg04,temp0,reg01,reg05,temp1,mask4,4 lwz reg15,12(src) MERGE_nBITS2 reg02,reg06,temp0,reg03,reg07,temp1,mask4,4 lwz reg12,16(src) MERGE_nBITS2 reg00,reg02,temp0,reg01,reg03,temp1,mask2,2 lwz reg16,20(src) MERGE_nBITS2 reg04,reg06,temp0,reg05,reg07,temp1,mask2,2 lwz reg13,24(src) MERGE_nBITS2 reg00,reg01,temp0,reg02,reg03,temp1,mask1,1 lwz reg17,28(src) MERGE_nBITS2 reg04,reg05,temp0,reg06,reg07,temp1,mask1,1 addi src,src,32 ;dcbt 0,src # fill cache line b exit2 b C2P_NI_mid C2P_NI_loop stwu reg10,4(plane7) MERGE_16BITS2 reg00,reg02,temp0,reg01,reg03,temp1 MERGE_16BITS2 reg04,reg06,temp0,reg05,reg07,temp1 lwz reg10,0(src) stwu reg14,4(plane3) MERGE_8BITS2 reg00,reg01,temp0,reg02,reg03,temp1 lwz reg14,4(src) stwu reg11,4(plane6) MERGE_8BITS2 reg04,reg05,temp0,reg06,reg07,temp1 lwz reg11,8(src) stwu reg15,4(plane2) MERGE_nBITS2 reg00,reg04,temp0,reg01,reg05,temp1,mask4,4 lwz reg15,12(src) stwu reg12,4(plane5) MERGE_nBITS2 reg02,reg06,temp0,reg03,reg07,temp1,mask4,4 lwz reg12,16(src) stwu reg16,4(plane1) MERGE_nBITS2 reg00,reg02,temp0,reg01,reg03,temp1,mask2,2 lwz reg16,20(src) stwu reg13,4(plane4) MERGE_nBITS2 reg04,reg06,temp0,reg05,reg07,temp1,mask2,2 lwz reg13,24(src) stwu reg17,4(plane0) MERGE_nBITS2 reg00,reg01,temp0,reg02,reg03,temp1,mask1,1 lwz reg17,28(src) addi src,src,32 dcbt 0,src # fill cache line MERGE_nBITS2 reg04,reg05,temp0,reg06,reg07,temp1,mask1,1 C2P_NI_mid stwu reg00,4(plane7) MERGE_16BITS2 reg10,reg12,temp0,reg11,reg13,temp1 MERGE_16BITS2 reg14,reg16,temp0,reg15,reg17,temp1 lwz reg00,0(src) stwu reg04,4(plane3) MERGE_8BITS2 reg10,reg11,temp0,reg12,reg13,temp1 lwz reg04,4(src) stwu reg01,4(plane6) MERGE_8BITS2 reg14,reg15,temp0,reg16,reg17,temp1 lwz reg01,8(src) stwu reg05,4(plane2) MERGE_nBITS2 reg10,reg14,temp0,reg11,reg15,temp1,mask4,4 lwz reg05,12(src) stwu reg02,4(plane5) MERGE_nBITS2 reg12,reg16,temp0,reg13,reg17,temp1,mask4,4 lwz reg02,16(src) stwu reg06,4(plane1) MERGE_nBITS2 reg10,reg12,temp0,reg11,reg13,temp1,mask2,2 lwz reg06,20(src) stwu reg03,4(plane4) MERGE_nBITS2 reg14,reg16,temp0,reg15,reg17,temp1,mask2,2 lwz reg03,24(src) stwu reg07,4(plane0) MERGE_nBITS2 reg10,reg11,temp0,reg12,reg13,temp1,mask1,1 lwz reg07,28(src) addi src,src,32 dcbt 0,src # fill cache line MERGE_nBITS2 reg14,reg15,temp0,reg16,reg17,temp1,mask1,1 bdnz C2P_NI_loop stwu reg10,4(plane7) stwu reg11,4(plane6) stwu reg12,4(plane5) stwu reg13,4(plane4) stwu reg14,4(plane3) stwu reg15,4(plane2) stwu reg16,4(plane1) stwu reg17,4(plane0) ; lwz r2,0(r1) ; lmw r11,4(r1) ; addi r1,r1,(32-10)*4 exit2 popgpr epilog ; blr ; .type C2P_NI,@function ; .size C2P_NI,$-C2P_NI ;##############################################################################