PowerUp-to-date

2. Status of the Escana-G3-project

»Braunschweig, December 22, 1998
Status of the G3-project!
Out of time considerations we had planned to implement a simplified memory
interface that would enable us to test the board as well as present it at the
Computer '98 show. This simplified interface did not feature ZorroIII bus
mastering. Since no prototype could be built in time for the show we went ahead
and implemented the full memory controller right away.
Our initial plans had been to do the full implementation once we have a working
prototype and the actual production begins. Implementing the memory interface
now presented us with a few problems that had to be addressed first, but this
also means that we will not have to face these problems later.
Another reason for doing the memory interface earlier is the fact that we now
have access to a SUN UltraSPARC that offers much greater resources for Verilog
simulations than the PC did that was used for that purpose up to now. However,
the Christmas season and new year's celebrations mean that the first prototypes
will not go into production until some time in January.
To sum things up: we are a little behind schedule (although not as far as one
might think based on the fact that there are still no prototypes available). We
ask for your understanding, especially since the memory interface is a
technologically very sophisticated solution. However, our goal remains to be
shipping the first production boards by the end of the first quarter.«