/* $Id: libcall_m68k.h,v 1.5 1996/10/24 01:35:57 aros Exp $ */ #ifndef GCC_LIBCALL_H #define GCC_LIBCALL_H /* Include aros/libcall.h first so that I can #undef the LP macros. */ #ifndef AROS_MACHINE_H # include #endif #ifndef AROS_LIBCALL_H # include #endif #ifndef AROS_RT_H # include #endif #define __RA0(type,name) \ type name(void) { /* How to build registerized parameters with gcc: The trick of those macros here is to define local register variables in the function that get initialized with an empty assembler template. Since the empty template is the first instruction in the function the registers still hold the correct values. To free the register later in the function it's necessary to copy the register variable into a normal one. It's possible that this will break sometimes in the future (likely when gcc gets _real_ registerized parameters) but changing those macros to adopt to that is simple. */ #define __RA1(type,name,type1,name1,reg1) \ type name(void) \ { \ register type1 __##name1 __asm(reg1); \ type1 name1=({asm("":"=r"(__##name1));__##name1;}); #define __RA2(t,n,t1,n1,r1,t2,n2,r2) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2));__##n1;});\ t2 n2=__##n2; #define __RA3(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; #define __RA4(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; #define __RA5(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ register t5 __##n5 __asm(r5); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4),"=r"(__##n5));__##n1;});\ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; \ t5 n5=__##n5; #define __RA6(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5,t6,n6,r6) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ register t5 __##n5 __asm(r5); \ register t6 __##n6 __asm(r6); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4),"=r"(__##n5), \ "=r"(__##n6));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; \ t5 n5=__##n5; t6 n6=__##n6; #define __RA7(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5,t6,n6,r6,t7,n7,r7) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ register t5 __##n5 __asm(r5); \ register t6 __##n6 __asm(r6); \ register t7 __##n7 __asm(r7); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4),"=r"(__##n5), \ "=r"(__##n6),"=r"(__##n7));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; \ t5 n5=__##n5; t6 n6=__##n6; t7 n7=__##n7; #define __RA8(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5,t6,n6,r6,t7,n7,r7,t8,n8,r8) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ register t5 __##n5 __asm(r5); \ register t6 __##n6 __asm(r6); \ register t7 __##n7 __asm(r7); \ register t8 __##n8 __asm(r8); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4),"=r"(__##n5), \ "=r"(__##n6),"=r"(__##n7), \ "=r"(__##n8));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; \ t5 n5=__##n5; t6 n6=__##n6; t7 n7=__##n7; \ t8 n8=__##n8; #define __RA9(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5,t6,n6,r6,t7,n7,r7,t8,n8,r8,t9,n9,r9) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ register t5 __##n5 __asm(r5); \ register t6 __##n6 __asm(r6); \ register t7 __##n7 __asm(r7); \ register t8 __##n8 __asm(r8); \ register t9 __##n9 __asm(r9); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4),"=r"(__##n5), \ "=r"(__##n6),"=r"(__##n7),"=r"(__##n8), \ "=r"(__##n9));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; \ t5 n5=__##n5; t6 n6=__##n6; t7 n7=__##n7; \ t8 n8=__##n8; t9 n9=__##n9; #define __RA10(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5,t6,n6,r6,t7,n7,r7,t8,n8,r8,t9,n9,r9,t10,n10,r10) \ t n(void) \ { \ register t1 __##n1 __asm(r1); \ register t2 __##n2 __asm(r2); \ register t3 __##n3 __asm(r3); \ register t4 __##n4 __asm(r4); \ register t5 __##n5 __asm(r5); \ register t6 __##n6 __asm(r6); \ register t7 __##n7 __asm(r7); \ register t8 __##n8 __asm(r8); \ register t9 __##n9 __asm(r9); \ register t10 __##n10 __asm(r10); \ t1 n1=({asm("":"=r"(__##n1),"=r"(__##n2), \ "=r"(__##n3),"=r"(__##n4),"=r"(__##n5), \ "=r"(__##n6),"=r"(__##n7),"=r"(__##n8), \ "=r"(__##n9),"=r"(__##n10));__##n1;}); \ t2 n2=__##n2; t3 n3=__##n3; t4 n4=__##n4; \ t5 n5=__##n5; t6 n6=__##n6; t7 n7=__##n7; \ t8 n8=__##n8; t9 n9=__##n9; t10 n10=__##n10; #ifndef __AROS_SLIB_ENTRY # define __AROS_SLIB_ENTRY(n,s) _##s##_##n #endif #define __AROS_LH0(t,n,bt,bn,o,s) \ __RA1(t,__AROS_SLIB_ENTRY(n,s),bt,bn,A6) #define __AROS_LH1(t,n,a1,bt,bn,o,s) \ __RA2(t,__AROS_SLIB_ENTRY(n,s),a1,bt,bn,A6) #define __AROS_LH2(t,n,a1,a2,bt,bn,o,s) \ __RA3(t,__AROS_SLIB_ENTRY(n,s),a1,a2,bt,bn,A6) #define __AROS_LH3(t,n,a1,a2,a3,bt,bn,o,s) \ __RA4(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,bt,bn,A6) #define __AROS_LH4(t,n,a1,a2,a3,a4,bt,bn,o,s) \ __RA5(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,bt,bn,A6) #define __AROS_LH5(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) \ __RA6(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,a5,bt,bn,A6) #define __AROS_LH6(t,n,a1,a2,a3,a4,a5,a6,bt,bn,o,s) \ __RA7(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,a5,a6,bt,bn,A6) #define __AROS_LH7(t,n,a1,a2,a3,a4,a5,a6,a7,bt,bn,o,s) \ __RA8(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,a5,a6,a7,bt,bn,A6) #define __AROS_LH8(t,n,a1,a2,a3,a4,a5,a6,a7,a8,bt,bn,o,s) \ __RA9(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,a5,a6,a7,a8,bt,bn,A6) #define __AROS_LH9(t,n,a1,a2,a3,a4,a5,a6,a7,a8,a9,bt,bn,o,s) \ __RA10(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,a5,a6,a7,a8,a9,bt,bn,A6) #define __AROS_LH0I(t,n,bt,bn,o,s) \ __RA0(t,__AROS_SLIB_ENTRY(n,s)) #define __AROS_LH1I(t,n,a1,bt,bn,o,s) \ __RA1(t,__AROS_SLIB_ENTRY(n,s),a1) #define __AROS_LH2I(t,n,a1,a2,bt,bn,o,s) \ __RA2(t,__AROS_SLIB_ENTRY(n,s),a1,a2) #define __AROS_LH3I(t,n,a1,a2,a3,bt,bn,o,s) \ __RA3(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3) #define __AROS_LH4I(t,n,a1,a2,a3,a4,bt,bn,o,s) \ __RA4(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4) #define __AROS_LH5I(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) \ __RA5(t,__AROS_SLIB_ENTRY(n,s),a1,a2,a3,a4,a5) /* This is one way to call a function with registerized paramaters and gcc: I build a define that defines normal function calls into one of those LC0()-Makros for expansion directly into the source code. They work as follows: First I copy the arguments of the function into normal variables. Second I copy those variables into the appropriate registers. (I cannot write them directly into those registers because this locks the register and one of the arguments may be a function call that needs it.) Third I call the assembler function with registers as arguments. Fourth I return the result. (The casting of the long is necessary to make void work). Prototype stylish Macros are also possible (using __inline functions instead of defines) but they need more system ressources to compile, more complicated Makefiles (gcc cannot inline without optimization) and cannot use local library bases. */ #define __LC0(type,name,basetype,basename,offset,system) \ ({ \ APTR __a6 = (basename); \ register long __d0 __asm(D0); \ { \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #offset ":W)" \ :"=r"(__d0) \ :"r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (type)__d0; \ }) #define __LC1(t,n,t1,n1,r1,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ APTR __a6 = (bn); \ register long __d0 __asm(D0); \ { \ register long ___n1 __asm(r1) = (long)__n1; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ :"=r"(__d0) \ :"r"(___n1),"r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (t)__d0; \ }) #define __LC2(t,n,t1,n1,r1,t2,n2,r2,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ t2 __n2 = (n2); \ APTR __a6 = (bn); \ register long __d0 __asm(D0); \ { \ register long ___n1 __asm(r1) = (long)__n1; \ register long ___n2 __asm(r2) = (long)__n2; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ :"=r"(__d0) \ :"r"(___n1),"r"(___n2),"r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (t)__d0; \ }) #define __LC3(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ t2 __n2 = (n2); \ t3 __n3 = (n3); \ APTR __a6 = (bn); \ register long __d0 __asm(D0); \ { \ register long ___n1 __asm(r1) = (long)__n1; \ register long ___n2 __asm(r2) = (long)__n2; \ register long ___n3 __asm(r3) = (long)__n3; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ :"=r"(__d0) \ :"r"(___n1),"r"(___n2),"r"(___n3), \ "r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (t)__d0; \ }) #define __LC4(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ t2 __n2 = (n2); \ t3 __n3 = (n3); \ t4 __n4 = (n4); \ APTR __a6 = (bn); \ register long __d0 __asm(D0); \ { \ register long ___n1 __asm(r1) = (long)__n1; \ register long ___n2 __asm(r2) = (long)__n2; \ register long ___n3 __asm(r3) = (long)__n3; \ register long ___n4 __asm(r4) = (long)__n4; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ :"=r"(__d0) \ :"r"(___n1),"r"(___n2),"r"(___n3), \ "r"(___n4),"r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (t)__d0; \ }) #define __LC5(t,n,t1,n1,r1,t2,n2,r2,t3,n3,r3,t4,n4,r4,t5,n5,r5,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ t2 __n2 = (n2); \ t3 __n3 = (n3); \ t4 __n4 = (n4); \ t5 __n5 = (n5); \ APTR __a6 = (bn); \ register long __d0 __asm(D0); \ { \ register long ___n1 __asm(r1) = (long)__n1; \ register long ___n2 __asm(r2) = (long)__n2; \ register long ___n3 __asm(r3) = (long)__n3; \ register long ___n4 __asm(r4) = (long)__n4; \ register long ___n5 __asm(r5) = (long)__n5; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ :"=r"(__d0) \ :"r"(___n1),"r"(___n2),"r"(___n3), \ "r"(___n4),"r"(___n5),"r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (t)__d0; \ }) /* Special: Preserves all registers (type must be void) */ #define __LC0P(t,n,bt,bn,o,s) \ ({ \ APTR __a6 = (bn); \ { \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ ::"r"(___a6):"memory"); \ } \ }) #define __LC1P(t,n,t1,n1,r1,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ APTR __a6 = (bn); \ { \ register long ___n1 __asm(r1) = (long)__n1; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("jsr a6@(-6*" #o ":W)" \ ::"r"(___n1),"r"(___a6):"memory"); \ } \ }) /* Needs special register */ #define __LC1S(t,n,t1,n1,r1,bt,bn,o,s) \ ({ \ t1 __n1 = (n1); \ APTR __a6 = (bn); \ register long __d0 __asm(D0); \ { \ long ___n1 = (long)__n1; \ register long ___a6 __asm(A6) = (long)__a6; \ asm volatile("exg %1," r1 ";jsr a6@(-6*" #o ":W);exg %1," r1 \ :"=r"(__d0) \ :"r"(___n1),"r"(___a6) \ :A0,A1,D0,D1,"memory"); \ } \ (t)__d0; \ }) #define __AROS_LCA(t,n,r) t,n,r #define __AROS_LC0(t,n,bt,bn,o,s) __LC0(t,n,bt,bn,o,s) #define __AROS_LC0P(t,n,bt,bn,o,s) __LC0(t,n,bt,bn,o,s) #define __AROS_LC1(t,n,a1,bt,bn,o,s) __LC1(t,n,a1,bt,bn,o,s) #define __AROS_LC1P(t,n,a1,bt,bn,o,s) __LC1(t,n,a1,bt,bn,o,s) #define __AROS_LC1S(t,n,a1,bt,bn,o,s) __LC1(t,n,a1,bt,bn,o,s) #define __AROS_LC1I(t,n,a1,bt,bn,o,s) __LC1(t,n,a1,bt,bn,o,s) #define __AROS_LC2(t,n,a1,a2,bt,bn,o,s) __LC2(t,n,a1,a2,bt,bn,o,s) #define __AROS_LC2I(t,n,a1,a2,bt,bn,o,s) __LC2(t,n,a1,a2,bt,bn,o,s) #define __AROS_LC3(t,n,a1,a2,a3,bt,bn,o,s) __LC3(t,n,a1,a2,a3,bt,bn,o,s) #define __AROS_LC3I(t,n,a1,a2,a3,bt,bn,o,s) __LC3(t,n,a1,a2,a3,bt,bn,o,s) #define __AROS_LC4(t,n,a1,a2,a3,a4,bt,bn,o,s) __LC4(t,n,a1,a2,a3,a4,bt,bn,o,s) #define __AROS_LC4I(t,n,a1,a2,a3,a4,bt,bn,o,s) __LC4(t,n,a1,a2,a3,a4,bt,bn,o,s) #define __AROS_LC5(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) __LC5(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) #define __AROS_LC5I(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) __LC5(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) #define __AROS_LC8(t,n,a1,a2,a3,a4,a5,a6,a7,a8,bt,bn,o,s) \ __LC8(t,n,a1,a2,a3,a4,a5,a6,a7,a8,bt,bn,o,s) #define __AROS_LC9(t,n,a1,a2,a3,a4,a5,a6,a7,a8,a9,bt,bn,o,s) \ __LC9(t,n,a1,a2,a3,a4,a5,a6,a7,a8,a9,bt,bn,o,s) #ifdef __AROS_LP0 #undef __AROS_LP0 #endif #define __AROS_LP0(t,n,bt,bn,o,s) #ifdef __AROS_LP1 #undef __AROS_LP1 #endif #define __AROS_LP1(t,n,a1,bt,bn,o,s) #ifdef __AROS_LP1I #undef __AROS_LP1I #endif #define __AROS_LP1I(t,n,a1,bt,bn,o,s) #ifdef __AROS_LP2 #undef __AROS_LP2 #endif #define __AROS_LP2(t,n,a1,a2,bt,bn,o,s) #ifdef __AROS_LP2I #undef __AROS_LP2I #endif #define __AROS_LP2I(t,n,a1,a2,bt,bn,o,s) #ifdef __AROS_LP3 #undef __AROS_LP3 #endif #define __AROS_LP3(t,n,a1,a2,a3,bt,bn,o,s) #ifdef __AROS_LP3I #undef __AROS_LP3I #endif #define __AROS_LP3I(t,n,a1,a2,a3,bt,bn,o,s) #ifdef __AROS_LP4 #undef __AROS_LP4 #endif #define __AROS_LP4(t,n,a1,a2,a3,a4,bt,bn,o,s) #ifdef __AROS_LP4I #undef __AROS_LP4I #endif #define __AROS_LP4I(t,n,a1,a2,a3,a4,bt,bn,o,s) #ifdef __AROS_LP5 #undef __AROS_LP5 #endif #define __AROS_LP5(t,n,a1,a2,a3,a4,a5,bt,bn,o,s) #ifdef __AROS_LP6 #undef __AROS_LP6 #endif #define __AROS_LP6(t,n,a1,a2,a3,a4,a5,a6,bt,bn,o,s) #ifdef __AROS_LP7 #undef __AROS_LP7 #endif #define __AROS_LP7(t,n,a1,a2,a3,a4,a5,a6,a7,bt,bn,o,s) #ifdef __AROS_LP8 #undef __AROS_LP8 #endif #define __AROS_LP8(t,n,a1,a2,a3,a4,a5,a6,a7,a8,bt,bn,o,s) #ifdef __AROS_LP9 #undef __AROS_LP9 #endif #define __AROS_LP9(t,n,a1,a2,a3,a4,a5,a6,a7,a8,a9,bt,bn,o,s) #define __AROS_ABS_CALL3(type,vec,n1,r1,n2,r2,n3,r3)\ ({ \ long __n1 = (long)(n1); \ long __n2 = (long)(n2); \ long __n3 = (long)(n3); \ long __vec= (long)(vec); \ register long __d0 __asm(D0); \ { \ register long ___n1 __asm(r1) = __n1; \ register long ___n2 __asm(r2) = __n2; \ register long ___n3 __asm(r3) = __n3; \ asm volatile("jsr %1@" \ :"=r"(__d0):"a"(__vec), \ "r"(___n1),"r"(___n2),"r"(___n3) \ :A0,A1,D0,D1,"memory"); \ } \ (type)__d0; \ }) #define __AROS_LVO_CALL0(type,offset,vec) \ __LC0(type,,long,vec,offset,) #define __AROS_LVO_CALL1(type,offset,vec,n1,r1) \ __LC1(type,,long,(long)(n1),r1,long,vec,offset,) #define __AROS_LVO_CALL2(type,offset,vec,n1,r1,n2,r2) \ __LC2(type,,long,(long)(n1),r1,long,(long)(n2),r2,long,vec,offset,) #define __AROS_LVO_CALL3(type,offset,vec,n1,r1,n2,r2,n3,r3) \ __LC3(type,,long,(long)(n1),r1,long,(long)(n2),r2,long,(long)(n3),r3,long,vec,offset,) #define __AROS_LVO_CALL4(type,offset,vec,n1,r1,n2,r2,n3,r3,n4,r4) \ __LC4(type,,long,(long)(n1),r1,long,(long)(n2),r2,long,(long)(n3),r3,long,(long)(n4),r4,long,vec,offset,) /* Finally the registers */ #define D0 "d0" #define D1 "d1" #define D2 "d2" #define D3 "d3" #define D4 "d4" #define D5 "d5" #define D6 "d6" #define D7 "d7" #define A0 "a0" #define A1 "a1" #define A2 "a2" #define A3 "a3" #define A4 "a4" #define A5 "a5" #define A6 "a6" #define __AROS_LHA(a,b,c) a,b,c #define __AROS_LPA(a,b,c) a,b,c #define __AROS_FUNC_INIT #define __AROS_FUNC_EXIT } #define __AROS_BASE_EXT_DECL(a,b) #endif