@database BBCpuUpgrade.guide @master BBCpuUpgrade1.0.guide @$VER: 1.0 @author "Remi Lenoir" @(c) "(C) Copyright 1995 Remi Lenoir" @remark Created with Heddley v1.1 (c) Edd Dumbill 1994 @node "Main" "The A2386SX BridgeBoard CPU upgrade guide" BBCpuUpgrade 1.0 The Commodore A2386SX BridgeBoard CPU Upgrade Guide¹ Copyright © 1995 Remi Lenoir All Rights Reserved @{" Distribution           " link "Distribution" 0} distribution @{" Introduction           " link "Introduction" 0} what is this guide ? @{" The 386SX Family       " link "The 386SX Family" 0} basic information @{" TI486SXLC2-50          " link "TI486SXLC2-50" 0} a detailed look @{" Commercial products    " link "Commercial products" 0} ready to use @{" Do it yourself         " link "Do it yourself" 0} the iron solder way @{" Configuration          " link "Configuration" 0} cache control @{" Performance            " link "Performance" 0} what you can expect @{" Problems               " link "Problems" 0} what you did not expect @{" Enhancements           " link "Enhancements" 0} going further @{" Pointers               " link "Pointers" 0} additional information @{" Requirements           " link "Requirements" 0} what you need @{" Disclaimer             " link "Disclaimer" 0} @{" Credits                " link "Credits" 0} ;-) @{" Author                 " link "Author" 0} Who ? ¹Will give you the right to display the coveted "Intel Outside" logo... @endnode @node "Distribution" "Distribution" @{b}Distribution@{ub} BBCpuUpgrade is FREEWARE. It is not public domain. The author gives permission for BBCpuUpgrade to be freely distributed providing that copying charges remain moderate and that no modification is made to the original distribution. Permission is granted to include this package in Public-Domain collections, especially in Fred Fishs Amiga Disk Library and Aminet (including CD ROM versions). If you want to include BBCpuUpgrade in a commercial product, please contact me. @endnode @node "Introduction" "Introduction" @{b}Introduction@{ub} If you are the owner of a stock Commodore A2386SX BridgeBoard, you will have noticed that, also it is a very nice and helpful device, it lacks the horsepower needed to comfortably run "heavy" software even if the software is very well thought, written and optimized like windows... NOT! The primary reason is that its 386SX CPU is not a speed demon anymore and is kind of outdated for windows-like applications. The other reason is that the architecture of the BridgeBoard is old (No external cache, ISA bus only, 16bit data path to memory). Thankfully, the 386SX was very popular in the PC notebook market mainly because it was the first -I think- to exist in a low power version (386SL). With the appearance of more powerful 80x86 chips, the demand for more powerful notebooks grew. The high end notebooks, not that concerned by the price problems, migrated to 486DX/DX2. The problem was the low end notebooks that could not afford these chips and the new architecture (new chip-set) that they required, not to mention the effort needed by that redesign that only a few Asian clone makers could support (technically and financially). This led to the design of pin compatible (same cheap PQFP package) derivatives that progressively adopted some of the features of the DX family (internal cache memory, clock doubling/tripling cores) when the technology allowed them to do so at an acceptable price. Still, to keep the cost down and retain compatibility with older design, they do not have the internal floating point unit and rely on the 387SX. Today, a system built around the most powerful 386SX derivative (IBM486SLC3) should perform closely to a 486DX2-50 desktop machine. Not bad at all and enough for most tasks. The rest of this guide will present you the various ways of upgrading the CPU of your BridgeBoard using both commercial and self made upgrades, will point out problems, provide some solutions, tell you what performance you can expect and hopefully help you make up your mind about what you want to do. Have fun, Remi. @endnode @node "The 386SX Family" "The 386SX Family" @{b}The 386SX Family@{ub} Before we start going into the details of each solutions, I would like you to be a little more familiar with the 386SX chip and the various derivatives that were developed. Note that the following summary does not pretend to be exhaustive but rather informative. INTEL 386SX: Originally developed by INTEL, it's a cut-down version of the 386DX. It has the same internal architecture but has a 16bit external data bus and a 24bit address bus (16MB address space). This allows the chip to fit in a 100 pin PQFP (Plastic) package instead of a PGA package thus leading to the original price difference. Note that this chip is (was?) also manufactured by AMD. INTEL 386SL: Same as above with the addition of power management features. This allows part or all of the chip to be put in stand-by or stopped under software and/or hardware control. Especially useful for battery operated applications (palmtop, ...). IBM 386SLC: Same as above with the addition of an internal cache. Note that if the side of the cache connected to the external bus is 16bit wide, the side connected to the CPU is 32bit wide. The cache is 8KB in size, two-way set associative, write-thru. Also, the instruction set was optimized (some instructions executes in fewer clock cycles). IBM 486SLC: Same as above but the cache size was increased to 16KB and its architecture was changed to four-way set associative. Although I don't have the data sheet of the IBM chips, I suppose the 486SLC series has a 486 compatible core (instruction set and register set compatible). IBM 486SLC2: Same as 486SLC with a clock-doubled core. IBM 486SLC3: Same as 486SLC with a clock-tripled core. Cyrix 486SLC-25: It is 486SX instruction set (and register set I suppose) compatible and has a 1KB cache. Cyrix 486SLC2-50: Same as above with a clock-doubled core. Texas Instruments TI486SXLC2-050: It has 486-compatible instruction set and register set, an 8KB two-way set associative cache, clock doubled core, highly optimized variable length pipeline and a hard wired multiplier. Like the Cyrix chip, it has a 386SX compatible bus interface. From what I understood, Texas Instruments licensed the core from Cyrix and added its own cache. @endnode @node "TI486SXLC2-50" "TI486SXLC2-50" @{b}TI486SXLC2-50@{ub} We are going to take a detailed look at one of this enhanced 386SX to outline the differences with the standard 386SX. You could first start to take a look at the @{" block diagram " link "TI486SXLC2-50diagram.iff/main" 0}. A new enhanced core The core is 486 instruction set and register set compatible. It has a new highly optimized, variable-length pipeline, an on-chip 16bit hardware (instead of micro-coded) multiplier. It is fully static so that the clock can be stopped and/or -dynamically- scaled to the desired value (see power management later in that section). Clock-doubling The core can be operated at the standard frequency -16, 20 or 25Mhz depending on its rating- but also at twice that frequency thanks to an on-chip PLL. Note that the external bus always operates at the normal frequency. On-chip cache It includes an 8K-byte, write-through unified instruction and data cache configured as two-way set associative. The same footprint but... some unused pins were used to add new signals to control the added features. Two pins are now used for power management (/SUSP and /SUSPA), two others become cache-interface signals (/FLUSH and /KEN) another two are used for System Management Mode signals (/SMADS and /SMI). Please take a look at the @{" pinout " link "TI486SXLC2-50pinout.iff/main" 0} and the @{" functional signal groupings " link "TI486SXLC2-50signals.iff/main" 0}. Power management A very interesting feature for energy-efficient and/or battery powered systems. It includes System management mode (SMM), suspend mode, dynamic clock scaling and a static core that permits clock-stop state. State after RESET After RESET, the chip is configured in such a way that all its new features are disabled to maintain total compatibility with the original 386SX. Later, the software will configure and enable the features it needs. Additional registers A set of new registers was added to control the new features of the chip. These registers are used to control the clock-doubled operation, the on-chip cache operation, power management features and system management mode. The clock-doubling, cache, power-management and SMM features can be enabled or disabled by writing to these registers. Registers: Configuration Control 0 (CCR0) Configuration Control 1 (CCR1) Address Region 1 (ARR1) Address Region 2 (ARR2) Address Region 3 (ARR3) Address Region 4 (ARR4) CCR0 Bit Definition: Bit Number Bit Name Description 0 NC0 Non-cacheable 1MB boundaries: if 1, sets the first 64KB at each 1MB boundary as noncacheable. 1 NC1 Noncacheable upper memory area: if 1, sets 640KB to 1MB memory as noncacheable. 2 A20M Enable /A20M pin if 1, enables /A20M, otherwise pin is ignored. 3 KEN Enable /KEN pin: if 1, enables /KEN, otherwise pin is ignored. 4 FLUSH Enable /FLUSH pin: if 1, enables /FLUSH, otherwise pin is ignored. 5 BARB Enable cache flush during hold: if 1, enables flushing of the internal cache when hold state is entered. 6 CKD Enable clock-double: if 1, enables clock-doubled mode if 0, disables clock-doubled mode 7 SUS Enable suspend pins: if 1, enables /SUSP and /SUSPA. if 0, /SUSPA floats and /SUSP is ignored. The CCR1 register is used to set up internal cache operation and system management mode. The ARR registers are used to define the location and size of the memory regions associated with the internal cache. The complete information can be found in the Reference Guide (See @{" pointers " link "Pointers" 0}). @endnode @node "Commercial products" "Commercial Products" @{b}Commercial Products@{ub} There are a number of commercial products that were developed to upgrade the aging 386SX based computers. The following list tries to give you an overview of what exists but does not pretend to be exhaustive. Also, it is accurate to the best of my knowledge but I can not guarantee that there are no mistakes or omissions. @{b}Cyrix:@{ub} Cx486SRx2 This is the most well-known product in the Amiga community. It is based on Cyrix's Cx486 core that features clock-doubling, on chip 1KB cache, single instruction execution and a hardware multiplier. It is known to work well and is very popular due to its simple installation. The @{" Cx486SRx2 " link "CyrixSRx2photo.iff/main" 0} snaps onto the surface mounted 386SX making the @{" installation " link "CyrixSRx2install.iff/main" 0} very easy (no soldering or chip removing). Some care must be taken to allow @{" airflow " link "CyrixSRx2dimension.iff/main" 0} around the upgrade. Note that not all the 386SX support the snapping method. The reason is that the first 386SX lack the FLOAT pin that, when activated, forces the chip to stop and tri-state all its outputs. Cyrix provides a free test program that tells you if your system can be upgraded (contact Cyrix's technical support). @{b}Evergreen:@{ub} Evergreen manufactures a large range of products from 286 to 486DX upgrades. Only the 386SX upgrades will be presented here. Rev To 486 SX2+ One model is based on Texas Instruments 486SXLC2-50 processor (see @{" the 386SX family" link "The 386SX Family" 0} overview for specs). This upgrade consists of a @{" PCB " link "EvergreenSX2photo.iff/main" 0} on which the TI chip is soldered that snaps onto a surface mounted 386SX. Here are the mechanical @{" dimensions " link "EvergreenSX2dimension.iff/main" 0}. Another model is based on IBM 486SLC2 processor (see @{" the 386SX family " link "The 386SX Family" 0} overview for specs). This upgrade consists of PCB that contains the two big chips and some glue logic (and a 3.3V regulator I think). Like the TI upgrade, it snaps onto the surface mounted 386SX. Rev To 486 SX3+ It is based on IBM 486SLC3 processor (see @{" the 386SX family " link "The 386SX Family" 0} overview for specs). The upgrade consists of @{" PCB " link "EvergreenSX3photo.iff/main" 0} that contains the two big chips and some glue logic (and a 3.3V regulator I think). Like the TI upgrade, it snaps onto the surface mounted 386SX. Note that it exists in several versions: - a 16/48 and 25/50Mhz version - a 20/60 and 33/66Mhz version - a 25/75 version Note that not all the 386SX support the snapping method. The reason is that the first 386SX lack the FLOAT pin that, when activated, forces the chip to stop and three-state all its outputs. Evergreen provides a free test program that tells you if your system can be upgraded (contact Evergreen's technical support). @{b}Improve Technologies:@{ub} Improve Technologies manufactures several products including 286, 386SX and 386DX upgrades. Only the 386SX upgrade will be presented here. Be careful as all the upgrades are named "Make-it 486". Make-it 486 (386SX) I do not have any documentation on this upgrade except a photo of the upgrade. It is made of a @{" PCB " link "ImproveTechPhoto.iff/main" 0} that holds the enhanced processor as well as two little ICs. I guess it uses a TI chip and that, like the Evergreen upgrades, snaps onto the surface mounted 386SX, but I am not sure. Note that not all the 386SX support the snapping method. The reason is that the first 386SX lack the FLOAT pin that, when activated, forces the chip to stop and three-state all its outputs. @{b}IBM:@{ub} IBM manufacture its own upgrades for its range of PS2 systems, some of them being based on 386SX CPU's. As explained in the 386SX family overview, IBM manufactures its own CPU based on INTEL cores and so it is logic to find them in its CPU upgrades. Note that I don't have that much informations about the IBM upgrades except the one available on their BBS/Internet site. I have absolutely no idea if they would work on a BridgeBoard. 486SLC2 It is based on IBM 486SLC2 processor (see @{" the 386SX family " link "The 386SX Family" 0} overview for specs). The upgrade consists of PCB that contains the two big chips, some glue logic and a socket for the math coprocessor (and a 3.3V regulator I think). Like the other upgrades, it snaps onto the surface mounted 386SX. 486SLC3 It is based on IBM 486SLC3 processor (see @{" the 386SX family " link "The 386SX Family" 0} overview for specs). The upgrade consists of PCB that contains a socket for the math coprocessor (and a 3.3V regulator I think). Like the other upgrades, it snaps onto the surface mounted 386SX. @endnode @node "Do it yourself" "Do it yourself" @{b}Do it yourself@{ub} @{b}ATTENTION:@{ub} This section describes some modifications that require specific electronic/manual skills and equipment. This can be dangerous for your BridgeBoard if you attempt to modify it and make a mistake. @{b}BE CAREFUL !@{ub} There is a way to upgrade the BridgeBoard without buying a commercial product. It consists in removing the original 386SX CPU and soldering a new one instead. This implies, of course, that you are confident with your manual and electronic skills... but it is the only way to upgrade BridgeBoards that use a non "FLoaTable" CPU (See the @{" 386SX Compatibility " link "386SX compatibility" 0} section). The first task is to choose the CPU you want to put in. The first option is the @{" TI486SXLC2-50 " link "TI486SXLC2-50" 0} from Texas Instruments. I have upgraded my BridgeBoard with this chip and it has been working absolutely flawlessly for the past six months. The other option is the Cx486SLC2-50 from Cyrix. Although I don't have the data sheet, I have very good reason to think it can be used. Of course you will have to get the data sheet and make sure it can be done before doing anything. The following description is what I have done to upgrade my BridgeBoard. 1 - Locate pin 1 of the 386SX Locate and remember where pin 1 is located. It will be useful later... 2 - Remove the 386SX Here you have to carefully unsolder the original CPU. Keep in mind that the most valuable element involved in the process is the BridgeBoard's PCB. Don't worry about the Intel chip unless you want to make a 3D intel outside logo ;) 3 - Solder the new CPU Here we go, nothing terrible. Remember to put pin 1 at the correct place... 4 - Check, Verify, Check, Verify, ... Make sure everything is correct and that you do not have any short. Use a lens. Check again. 5 - Power on As the new features of the chip are disabled at reset, you do not need to worry about the configuration/compatibility yet. Do some checking to make sure everything is working as before. Anyway, if the machine boots you can be pretty sure it is OK. 6 - Install the software Install and setup the configuration software. If you bought the chip from TI you should get the configuration software from them. Play with it until you understand everything and when you are done, install the BBcpuclk program (see the @{" Clock problems " link "Clock problems" 0} section). You should now have a working clock doubling upgrade. Note: there is a freeware configuration program (see @{" Pointers " link "Pointers" 0} for where to get it) you can also use. It is targeted at the Cyrix chip but can also be used with the TI chip. See the @{" Configuration " link "Configuration" 0} section for an example. 7 - Add external cache control You can now implement the modification exposed in the @{" Enhancements " link "Enhancements" 0} section. It will prevent the cache from being flushed every refresh cycle and will substantially improve the performance. Remember to modify the software setup to use the /FLUSH pin instead of the BARB bit. Please refer to the @{" Configuration " link "Configuration" 0} section for information about how to configure the chip. Suggestion: The chip is quite hot when running in double-clock mode. I would advice to use a heat sink/fan to cool it. I personaly use one that is a fan combined with a heat sink which has an adhesive to stick it on top of the CPU. It works perfectly. @endnode @node "Configuration" "Configuration " @{b}Configuration@{ub} For compatibility reasons, the new features of the enhanced CPU's are disabled at RESET. Those new features can be activated at three different times. Early in the boot process by the BIOS, later in the boot process by programs launched in the CONFIG.SYS or AUTOEXEC.BAT files or during normal operation. The first option is unlikely to be used because it would require the modification or replacement of the BridgeBoard BIOS which is not impossible but not an easy task. The modification of the BIOS would also raise legal questions and the replacement by a standard BIOS would be likely to fail because of the BB peculiarities (JANUS, emulated Keyboard, etc...). Another option would be to modify or rewrite the Janus handler but this would not be an easy task either. This method is also not practicable for the CPU Upgrade vendors for the obvious reason that they can not modify everyone's BIOS. The second option is the one chosen by IBM and Evergreen for their upgrades. It consists of a driver that must be installed in the first line of the CONFIG.SYS file. It will stay in memory and allow you to later modify the setup with a program that you launch from the DOS prompt and that will "talk" to this driver. The third option is the one I use with the TI chip. A program is called in the AUTOEXEC.BAT that configures the chip. It sets-up the cache flush method, the non-cacheable areas (see the @{" Cache coherency " link "Cache coherency" 0} section) and starts the clock-doubler. Note that in order for the clock-doubler to work I have to call the BBcpuclk program before (see the @{" Clock problems " link "Clock problems" 0} section). Relevant part of my BIOS setup: VIDEO VGA/EGA VGA/EGA Shadow ENABLED BIOS Shadow ENABLED CPU configuration: As explained in the @{" Cache coherency " link "Cache coherency" 0} section, you will have to select a way to maintain the coherency of the CPU's cache. First there are areas that need to be configured as non cacheable (see below). Second you need tell the CPU what to do when another master controls the bus. Two options here. The software only method that consists in flushing the cache every time another master takes control of the bus. For that there is a bit (in the CYRIX and TI chips) called BARB that need to be set. The second -hardware- option is to control the flush by an external logic (see @{" Cache coherency " link "Cache coherency" 0} and @{" Enhancements " link "Enhancements" 0} sections). In that case there is a bit (in CYRIX and TI chips) called FLUSH that needs to be set. Notes: 1 - The information regarding the BARB and FLUSH bits is relevant to TI and CYRIX users. As I don't have the data sheet of the IBM chip, I don't know how things work with this chip. Any information is welcome. 2 - If your configuration software doesn't let you access the bits directly but provides you with a "high level" interface then you will have to make the relation between what is explained here and what your software proposes. However it is very likely that your software will automatically set the BARB bit as it doesn't expect you to use your iron solder... 3 - There is a public domain configuration software (with source code) for Cyrix CPUs. It can also be used with the TI chip (I tested it) although you have to be aware that CCR0 bit 6 that is clock double ON/OFF on the TI chip is cache direct mapped/2 way set associative in the Cyrix chip. In clear, configuring for direct mapped cache with a TI chip will start the clock doubler, configuring for 2 way set associative will stop the clock doubler (the TI chip can operate at either normal or double speed). See the @{" Pointers " link "Pointers" 0} section for where to get this program. Here is an example that works for my "Do it yourself" + external cache flush upgarded BridgeBoard (note the -cd option that starts the clock doubler): cyrix -f -xa000,128 -xc000,128 -cd The non-cacheable areas on my BridgeBoard are set this way: Non Cacheable Area 1: Starts at 0x000A0000 and is 128KB is size. This is the VGA board memory (I have an SVGA board). I think it includes the frame buffer memory and the board's BIOS. If this memory area is cached, the display is slightly trashed in graphic mode (both under DOS and windows). Non Cacheable Area 2: Starts at 0x000C0000 and is 128KB in size. This is the Janus memory. I think it includes the Janus handler and the dual port memory used to communicate with the Amiga. If this memory area is cached, AWRITE and AREAD hang. Non Cacheable Areas 3 and 4 are disabled. The PCPrefs program is configured as follow: Janus Handler Segment Load : D000 Janus Handler Shadowed : YES Monochrome Display Adapter Emulation : Disabled Color Display Adapter Emulation : Disabled Default BridgeBoard Video Mode : Color @endnode @node "Performance" "Performance" @{b}Performance@{ub} CPU Benchmarks: Norton: Norton SI 8.0 performance test Checkit: Checkit 3.0 performance test Backup: Backup 50Meg from the IDE hard disk using PKZIP (under DOS 5.0) A2386SX-25 with TI CPU: |--------|------------|------------|------------|------------| |386SX-25|TI486 @25Mhz|TI486 @50Mhz|TI486 @25Mhz|TI486 @50Mhz| | |+ BARB flush|+ BARB flush|+ ext flush |+ ext flush | --------|--------|------------|------------|------------|------------| Norton | 15.9 | 33.9 | 59.7 | 39.4 | 70.5 | --------|--------|------------|------------|------------|------------| Checkit | 4911 | 5262 | 6374 | 9895 | 16999 | --------|--------|------------|------------|------------|------------| Backup | 7mn18s | 6mn53s | 5mn33s | 4mn19s | 3mn01s | --------|--------|------------|------------|------------|------------| Systems: |-----------|---------------------------|--------------| | 386 | 486 | PENTIUM | |-----|-----|-----|------|------|-------|--------------| |SX-25|DX-33|DX-33|DX2-50|DX2-66|DX4-100|PNT-75|PNT-100| Ext Cache | 0KB | |256KB|256KB |256KB | 256KB |256KB | 512KB | ----------|-----|-----|-----|------|------|-------|------|-------| Norton | 15.9| 35.9| 71.2| 108.2| 144.3| | 237.7| 316.4 | ----------|-----|-----|-----|------|------|-------|------|-------| Checkit | 4911| |15785| 23164| 33609| 45214 | 59343| 78419 | ----------|-----|-----|-----|------|------|-------|------|-------| A mark of 154 (Norton) has been reported on an A2386SX BridgeBoard upgraded with a clock tripling Evergreen upgrade overclocked to 99Mhz. This lead me to think that a 75Mhz upgrade should perform a little better than a 486DX2-50. Input/Output Accesses: The I/O accesses are done thru the bus as opposed to the memory that is directly connected to the CPU. So the I/O performance (i.e. hard disk) not only depends on the CPU but also on the bus. The bus usually runs at a different speed and has a different path size than the CPU, meaning that the I/O performance of a machine (i.e. hard disk speed) will depend more on the bus than on the CPU (provided that the CPU is faster than the bus, as is usually the case). It is important to keep this in mind when looking at the performance. The disk accesses are not going to be much faster on a Pentium-100 than on a DX2-66 if the hard disk is IDE and connected through an ISA controller. Would they have a different type of bus, I made a test that is somewhat interesting... Checkit gave me a 954KB/sec on a Pentium-75 with a PCI Fast SCSI II interface and a SCSI disk. The same test gave me 1035KB/sec on my BridgeBoard with an IDE disk. Of course the problem is the -old- SCSI disk. This just reminds us that the system is only as fast as the slowest element in the chain. Using a fast bus (i.e. PCI) AND a fast interface (PCI Fast SCSI II) AND a fast hard disk (i.e. Fast SCSI II 7200 rpm disk, may be wide) will really speed up the system. The PC OS (well, I mean...) and PC software are usually very memory intensive and, unless you have an significant amount of RAM, make a heavy use of virtual memory which translates into hard disk accesses. For tasks that make heavy usage of the hard disk (windows, network server, unix, etc...) the bus/hard disk set-up is as important as the CPU. For tasks that make a heavy usage of the CPU (Image rendering, PCB/FPGA routers, signal processing, etc...) the bus/hard disk setup is not as critical. Conclusion: These upgrades clearly bring the BridgeBoard in the 486DX/DX2 class of machines. And their costs (between $100 and $300 as of this writing) are quite reasonable in regards to the performance and the comfort improvement they bring. @endnode @node "Problems" "Problems" @{b}Problems@{ub} @{" 386SX compatibility      " link "386SX compatibility" 0} Do you have an old CPU ? @{" Cache Coherency          " link "Cache coherency" 0} How to maintain it @{" Clock problems           " link "Clock problems" 0} Clock-doubling/tripling @{" FPU problems             " link "FPU problems" 0} Unsolved problems... @endnode @node "Enhancements" "Enhancements" @{b}Enhancements@{ub} Cache coherency As suggested in the @{" Cache Coherency " link "Cache coherency" 0} section, there is a better way of maintaining the coherency of the cache than flushing the cache during every hold state as done by Cyrix and Texas Instruments. This software only method doesn't distinguish between DMA *TO* memory and DMA *FROM* memory. This means that the cache is flushed even during DMA **FROM** memory although this DMA access doesn't invalidate the cache coherency. The BridgeBoard is using an old chip-set that refreshes the DRAM using a DMA channel. Refresh by DMA operates by reading the DRAM every 15us so if we could avoid flushing the cache every refresh cycle we would substantially improve the performance (and make a much better use of the cache). Texas Instruments proposes a simple hardware solution to that problem by providing a FLUSH pin. It is then the responsibility of an external logic to flush the cache whenever the cache coherency is jeopardized. This external logic has to activate the FLUSH input each time a DMA *TO* memory occurs. This is done by the following logic: |¯¯¯¯\\ +5V ------| | |¯¯¯¯\\ | |O----------| | /MEMW ------| | | |O--------- /FLUSH |____/ |----| | | |____/ HOLDA ------------------| I used a 74F00 that I soldered on top of U413 to fasten it to the board and get the power supplies. The pins of the gates are bent not to touch U413 and connected to the BridgeBoard using wire wrapping wire. The inputs of the unused gates are tied to VCC. Notes: - The / sign indicates an active low signal (TI doc. uses #). - The gates are 74F00 or anyother fast NAND gate. - /MEMW is the 16bit ISA bus write signal (see diagram below). - HOLDA is the CPU HOLDA pin (pin 3). - /FLUSH is the CPU (486SXLC2-50 only) /FLUSH pin (pin 30). The reason why this simple logic is not included in the CPU is that the CPU doesn't have access to the ISA Bus /MEMW signal. Once you did that, you have to enable the /FLUSH pin by setting the FLUSH bit in the CCR0 register. Of course you no longer have to set the BARB bit. ISA /MEMW signal: ______________________________________________| | | | | | | | | | A2386SX BridgeBoard |<- MOUNTING BRACKET | | | | | | |______________________________________________| |_____________| |______| |_____________| | 100 2 18 1 31 1 | AMIGA CONNECTOR AT CON XT CON The 16bit write signal (/MEMW) is located on pin C10 which is pin 10 on the AT connector on the @{fg shine}component@{fg text} side of the PCB. @endnode @node "Pointers" "Pointers" @{b}Pointers@{ub} Here is a list of places where you can find additional information. @{b}Literature@{ub} Texas Instruments: TI486SXLC and TI486SXL Microprocessors Reference Guide......SRZU006B TI486SXL Family Product Bulletin............................SRZB001 How to Upgrade a 386 based design with a TI486 CPU (App Note) IBM: ???? Cyrix: ???? @{b}Articles/Software@{ub} MicroComputer Journal, March/April 1995 "CPU Upgrades: The complete Story", p53/63 by TJ Byers cyrix100.zip (SimTel/msdos/sysutil/cyrix100.zip) -> Contains informations, advices and SOURCE CODE of a configuration program for the Cyrix chip (show how to access the special registers). @{b}Companies@{ub} IBM 3039 Cornwallis Drive, Bld 203 Research Triangle Park, NC 27709 USA Automated FAX system: 1 800 IBM 3395 BBS: 919 517 0001 ftp.pcco.ibm.com (same as BBS) Texas Instruments See your local TI representative Cyrix Corporation 2703 North Central Expressway Richardson, TX 75080 USA Tel: (214) 994 8388 Fax: (214) 699 9857 BBS: (214) 994 8610 Tech Support and Sales: Tel: 1 800 462 9749 tech_support@cyrix.com http://www.cyrix.com Improve Technologies 345 E. 800 S Orem, UT 84058 Tel: (801) 224 0088 Fax: (415) 286 3999 Evergreen Technologies 915 NW Eighth Street Corvalis, OR 97330-6211 USA Tel: (503) 757 0934 Fax: (503) 757 7350 BBS: (503) 752 9851 Brentwood Business Systems (Evergreen reseller) 4140 Brentwood Street Wheat ridge, CO 80033 USA Tel: 800 431 8542 / (303) 431 8542 Fax: (303) 431 6647 @endnode @node "Requirements" "Requirements" @{b}Requirements@{ub} - AmigaGuide V39 and OS3.0+ to see the pictures from AmigaGuide. - A Commodore A2386SX BridgeBoard. If you can't display the pictures correctly with your setup (Display, MultiView or AmigaGuide problem for example) get a good viewer like Viewtek (available on Aminet) and display the pictures from the WorkBench. For information, here is the system I use. A3000T 2MB Chip, 16MB Fast on MotherBoard, GVP 040 @28Mhz with 4MB. A2386SX-25, 8MB, Cyrix FastMath FPU (25Mhz) with the following customization: - Intel 386SX replaced by a TI486SXLC2-50. - External cache flush logic added. The A2386SX is equipped with: - An IDE/Serial/Parallel/Game controller and a 400MB IDE Hard Disk. - An ATI Wonder SVGA card. - An electronic monitor switch (/pub/aminet/hard/misc/BBSwitch1.0.lha). As for the software I use: - SXServ 1.6 from Frank Mariak (/pub/aminet/misc/emu/SXServ1.6.lha). - BBcpuclk1.0 (/pub/aminet/misc/emu/BBcpuclk1.0.lha). - The OEM configuration software from TI. The BridgeBoard system has also been working flawlessly in my stock A4000/40. @endnode @node "Disclaimer" "Disclaimer" @{b}Disclaimer@{ub} This document and its information is provided "as is" without warranty of any kind, either expressed or implied. The entire risk as to the accuracy of the information herein is assumed by you. The author does not warrant, guarantee, or make any representations regarding the use of, or the results of the use of, the information in terms of correctness, accuracy, reliability, currentness, or otherwise. In no event will the author be liable for direct, indirect, incidental, or consequential damages resulting from any defect in the informations even if he has been advised of the possibility of such damages. I wanted to add some humanity to this section but I couldn't find anything that really pleased me so, for now, it will stay this way... @endnode @node "Credits" "Credits" @{b}Credits@{ub} Amiga is a registered trademark of Commodore-Amiga, Inc. BridgeBoard and Janus are trademarks of Commodore-Amiga, Inc. Other names are trademarks of their associated owners. Thanks to those who reported problems, sent "Works great!" email and all the other persons who share information on the BridgeBoard. Special thanks to the following persons: - Brian J. Heyboer for providing me with the VL82C311 data-sheet and correcting my numerous English mistakes. - Peter Ouzts for BETA testing BBcpuclk on the Evergreen upgrade. - Gary S. Cooper for BETA testing BBcpuclk and pointing out the WRAPPER.SYS program. - Stewart Hunt for providing me with the Evergreen advertisement information. Remi. @endnode @node "Author" "Author" @{b}Author@{ub} I regularly check the comp.sys.amiga.emulations newsgroup of Usenet. Post any comments, suggestions, questions there and you will hear from me. Notes: - As I also speak French, I will be pleased to answer your questions en Français. - Last but not least, I am searching for the BridgeBoard development tools (Janus 2.1). Remi. @endnode @node "386SX compatibility" "386SX compatibility" @{b}386SX Compatibility@{ub} Not all the 386SX supports the upgrade. The reason is that when an upgrade is snapped onto a 386SX, it activates a pin of this CPU called FLT (FLoaT). This causes the CPU to stop and tri-state all its outputs allowing the upgrade to take control of the computer. The problem is that early versions of the INTEL and AMD 386SX-16 and 386SX-20 do not have this pin. Both Cyrix and Evergreen provide a free program that will tell you if your CPU has the FLT pin and thus is compatible with the upgrades (See @{" Pointers " link "Pointers" 0} for Cyrix and Evergreen addresses). @endnode @node "Cache coherency" "Cache Coherency" @{b}Cache Coherency@{ub} As explained earlier in the 386SX Family section, the enhanced 386SX processors added an on-chip cache to the standard 386SX architecture. The cache considerably boosts the performance, especially with  clock-doubled and clock-tripled cores, but at the cost of adding a problem: its coherency, that must be maintained. The coherency is broken when a location is written without the cache knowing about it. This happens in three cases: - In the IO sections where, by definition, the bits are set by the IO chips themselves. That's why the IO sections are never cached. - During DMA transfers **TO** the memory. - In dual-port memory sections like the one used to communicate with the Amiga. The first case is easy. The IO transfers are being issued by the CPU, the cache unit knows about them and ignores them. The second case is also easy to handle. The cache is invalidated every time the CPU enters the hold state (the state in which the CPU is during DMA). This however, doesn't distinguish between a DMA *TO* memory or *FROM* memory. Please refer to the @{" Enhancements " link "Enhancements" 0} section for a better -hardware- solution. The third case is solved by using special registers specially implemented in the enhanced 386SX CPU's to deal with this problem. Those registers can be used to define regions in which the cache is disabled. They are initialized before the cache is enabled. @endnode @node "Clock problems" "Clock problems" @{b}Clock Problems@{ub} With some upgrades, you are likely to encounter problems when trying to start the clock-doubler or clock-tripler of the CPU, the machine will hang. Two upgrades which have caused problems are the Evergreen Rev To 486 SX3+ (based on the IBM chip) and the Evergreen Rev To 486 SX2+ (based on the TI486SXLC2-50 chip). Note that the problems are not caused by Evergreen but by the chip themselves (more on that later). Note that I don't remember someone reporting similar problems with the Cyrix upgrade. In case you experience problems with a Cyrix upgrade, I would like to hear from you (see the @{" author " link "Author" 0} section). The Evergreen SLC3 upgrade uses an enhanced version of the 386SX developed by IBM. This enhanced version uses, among other things, a clock tripled core to improve the performance. The problem is that when used in a Bridgeboard, the CPU hangs when the clock tripler circuit is started. In other words, you can use the CPU at 16, 20 or 25Mhz (depending on which BridgeBoard you have) and take advantage of its internal 16KB cache but you can not take advantage of the clock tripler. Considering the price of the toy, it's pretty annoying. I was not able to determine the exact reason of the failure except that the IBM486SLC3 "doesn't like" the clock it receives from the BridgeBoard. What guided me to the solution is that the clock tripler operates properly when the BridgeBoard is configured with SYSTEM SPEED = LOW. The solution consists in giving a "better" clock to the CPU. How is this done ? This is done by modifying the configuration of the PC chip set used on the BridgeBoard. One of the chip (VL82C311) contains a unit that generates the CPU clock and the BUS clock. This unit is quite flexible and looks like this: TURBO ON/OFF | | | \\|/ |-----| |---------------------| | | | | \\ | |-----------| | MUX |----- CLK2 | \\| | \\| | / TCLK2 ----|---| NON-TURBO |-----| | /| DIVIDER | /|------ | | |-----------| /|\\ | | | DIVIDE RATIO (1, 2, 3, 4) Notes: - TCLK2 is the output of the oscillator from which the CPU clock is derived. - CLK2 is the CPU clock. In a standard 386SX it is divided by two before going to the core giving an operating frequency half of CLK2 (32Mhz for a 16Mhz system, 40Mhz for a 20Mhz one and 50Mhz for a 25Mhz one). As you can see, you have two ways of giving the CLK2 clock to the CPU. By going direct (TURBO option) or by going through the divider and choose a ratio of 1. When the BridgeBoard is configured as SYSTEM SPEED = HIGH (in BIOS SETUP), the unit is configured in TURBO mode, when SYSTEM SPEED = LOW, the unit is configured in NON TURBO with a divide ratio of 2 (half speed). The solution is to provide CLK2 by going through the divider with a ratio of 1 rather than using the TURBO mode. In theory it should be equivalent but the Evergreen upgrade does not operate reliably with the TURBO mode whereas it does with NON TURBO. I think the clock generated with the NON TURBO mode has faster rise time/fall time and/or less skew or something like this that keeps the clock tripler circuit happy. A small program that modifies the configuration of the PC chip set has to be executed BEFORE the clock tripler is started. Check out the Notes below to know where to get it. The clock tripler is started when the CPU is configured and this is done by the Evergreen configuration program launched in the CONFIG.SYS file. The problem is that I am anything but a PC specialist and I don't know how to write a .SYS program. Fortunately there is a utility called WRAPPER.SYS that will launch a .COM or .EXE program from the CONFIG.SYS file. Just insert the following line in the first line of your CONFIG.SYS file: DEVICE = WRAPPER.SYS BBcpuclk.com Then you can insert the call to the Evergreen configuration program. Notes: 1 - The above explanations are also true for the Evergreen SX2+ and, I think, for any CPU upgrade that uses the IBM or the Texas Intruments chip. 2 - I still don't know the exact reason why the CPU hangs when its clock does not go through the divider. I might take a closer look at that later but as everything is working... 3 - One user using the Evergreen SX2+ upgrade based on the TI chip has reported problems launching BBcpuclk with WRAPPER. For an unknown reason, it would not work. We can bypass the problem by not using the Evergreen program to configure the Upgrade. Instead we can use the public domain program written for the Cyrix chip as described in the @{" configuration " link "Configuration" 0} section. Do the following: (1) remove the Evergreen driver from CONFIG.SYS. (2) Launch BBcpuclk from AUTOEXEC.BAT. (3) Launch the Cyrix configuration program with the proper parameters from AUTOEXEC.BAT (After BBcpuclk). BBcpuclk.com: This program can be found on an Aminet archive (/misc/emu/BBcpuclk1.0.lha). BBcpuclk1.0 is Copyrighted (1995) by Remi Lenoir. WRAPPER.SYS: This program can be found on a SIMTEL archive (/msdos/bootutil/wrapsy10.zip). WRAPPER.SYS is Copyrighted (1992) by Philip B. Gardner. @endnode @node "FPU problems" "FPU problems" @{b}FPU problems@{ub} A number of problems involving the FPU (math coprocessor) have been reported. Some appears even without a CPU upgrade installed. @{fg shine}If you experience problems after installing an upgrade, try removing the FPU.@{fg text} Here is a quick list of problems that have been reported: Config : A2386SX + "Do it yourself" TI486SXLC2-50 upgrade + IIT XC87SLC-33 Behavior: The BB would sometime boot, sometime not. If it booted it would execute some programs fine and not some others (BB would hang). Cause : UNKNOWN. Config : A2386SX + Cyrix Cx486SRx2-50 upgrade + IIT XC87SLC-33 Behavior: Some systems OK, some other not. Cause : UNKNOWN. Config : A2386SX + Evergreen Rev To 486 SX3+ upgrade + Cyrix 83S87-25 Behavior: BB doesn't boot. Cause : UNKNOWN. @endnode