שתשת*********************************************************** * $VER: demo_i 1.3 * Revision history: * 1.3: * Fixed error in conditional assembly. * * 1.2: * name changed from 'custom.i' to 'demo.i' to avoid confusion * lf codes were added (thanks to howtocode5.txt!) * * 1.1: * cop2lc address was corrected * WaitVblank and WaitBlitter macros were added * * 1.0: * Initial release *********************************************************** * Custom chip register addresses * Custom equ $dff000 ; Custom chips base address bltddat equ $0000 ; Blitter Destination Data (DMA only) dmaconr equ $0002 ; DMA Enable Read vposr equ $0004 ; Vertical Beam Position Read vhposr equ $0006 ; Vert/Horiz Beam Position Read dskdatr equ $0008 ; Disk Data Read (DMA only) joy0dat equ $000a ; Joystick/Mouse Port 0 Data (read) joy1dat equ $000c ; Joystick/Mouse Port 1 Data (read) clxdat equ $000e ; Collision Data (read) adkconr equ $0010 ; Audio/Disk Control Read pot0dat equ $0012 ; Pot Port 0 Data Read pot1dat equ $0012 ; Pot Port 1 Data Read potgor equ $0016 ; Pot Port Data Read serdatr equ $0018 ; Serial Data Input and Status Read dskbytr equ $001a ; Disk Data Byte and Disk Status Read intenar equ $001c ; Interrupt Enable (read) intreqr equ $001e ; Interrupt Request (read) dskpt equ $0020 ; Disk Pointer (write) dskpth equ dskpt dskptl equ dskpt+2 dsklen equ $0024 ; Disk Data Length dskdat equ $0026 ; Disk DMA Write refptr equ $0028 ; Refresh Pointer (write) DON'T USE! vposw equ $002a ; Vert Beam Position Write DON'T USE! vhposw equ $002c ; Vert/Horiz Beam Pos Write DON'T USE! copcon equ $002e ; Coprocessor Control serdat equ $0030 ; Serial Data Output (write) serper equ $0032 ; Serial Period & Data Bit Control (write) potgo equ $0034 ; Pot Port Data (write) joytest equ $0036 ; JOY0DAT and JOY1DAT Write strequ equ $0038 ; Short Frame Vertical Strobe strvbl equ $003a ; Normal Vertical Blank Stobe strhor equ $003c ; Horizontal Sync Strobe strlong equ $003e ; Long Raster Strobe bltcon0 equ $0040 ; Blitter Control Register 0 (write) bltcon1 equ $0042 ; Blitter Control Register 1 (write) bltafwm equ $0044 ; Source A First Word Mask (write) bltalwm equ $0046 ; Source A Last Word Mask (write) bltcpt equ $0048 ; Blitter Source C Pointer (write) bltcpth equ bltcpt bltcptl equ bltcpt+2 bltbpt equ $004c ; Blitter Source B Pointer (write) bltbpth equ bltbpt bltbptl equ bltbpt+2 bltapt equ $0050 ; Blitter Source A Pointer (write) bltapth equ bltapt bltaptl equ bltapt+2 bltdpt equ $0054 ; Blitter Destination Pointer (write) bltdpth equ bltdpt bltdptl equ bltdpt+2 bltsize equ $0058 ; Blitter Start and Size (write) bltcmod equ $0060 ; Blitter Source C Modulo (write) bltbmod equ $0062 ; Blitter Source B Modulo (write) bltamod equ $0064 ; Blitter Source A Modulo (write) bltdmod equ $0066 ; Blitter Destination Modulo (write) bltcdat equ $0070 ; Blitter Source C Data (write) bltbdat equ $0072 ; Blitter Source B Data (write) bltadat equ $0074 ; Blitter Source A Data (write) dsksync equ $007e ; Disk Sync Pattern (write) cop1lc equ $0080 ; Copper Program Counter 1 (write) cop1lch equ cop1lc cop1lcl equ cop1lc+2 cop2lc equ $0084 ; Copper Program Counter 2 (write) cop2lch equ cop2lc cop2lcl equ cop2lc+2 copjmp1 equ $0088 ; Copper Jump Strobe 1 copjmp2 equ $0088 ; Copper Jump Strobe 2 copins equ $008c ; Copper Instruction Identity (write) diwstrt equ $008e ; Display Window Start (write) diwstop equ $0090 ; Display Window Stop (write) ddfstrt equ $0092 ; Display Data Fetch Start (write) ddfstop equ $0094 ; Display Data Fetch Stop (write) dmacon equ $0096 ; DMA Control (write) clxcon equ $0098 ; Collision Control (write) intena equ $009a ; Interrupt Enable (write) intreq equ $009c ; Interrupt Request (write) adkcon equ $009e ; Audio/Disk Control (write) aud0lc equ $00a0 ; Channel 0 Waveform Address (write) aud0lch equ aud0lc aud0lcl equ aud0lc+2 aud0len equ $00a4 ; Channel 0 Waveform Length (write) aud0per equ $00a6 ; Channel 0 Period (write) aud0vol equ $00a8 ; Channel 0 Volume (write) aud0dat equ $00aa ; Channel 0 Data (write) aud1lc equ $00b0 ; Channel 1 Waveform Address (write) aud1lch equ aud1lc aud1lcl equ aud1lc+2 aud1len equ $00b4 ; Channel 1 Waveform Length (write) aud1per equ $00b6 ; Channel 1 Period (write) aud1vol equ $00b8 ; Channel 1 Volume (write) aud1dat equ $00ba ; Channel 1 Data (write) aud2lc equ $00c0 ; Channel 2 Waveform Address (write) aud2lch equ aud2lc aud2lcl equ aud2lc+2 aud2len equ $00c4 ; Channel 2 Waveform Length (write) aud2per equ $00c6 ; Channel 2 Period (write) aud2vol equ $00c8 ; Channel 2 Volume (write) aud2dat equ $00ca ; Channel 2 Data (write) aud3lc equ $00d0 ; Channel 3 Waveform Address (write) aud3lch equ aud3lc aud3lcl equ aud3lc+2 aud3len equ $00d4 ; Channel 3 Waveform Length (write) aud3per equ $00d6 ; Channel 3 Period (write) aud3vol equ $00d8 ; Channel 3 Volume (write) aud3dat equ $00da ; Channel 3 Data (write) bpl1pt equ $00e0 ; Bitplane 1 Pointer (write) bpl1pth equ bpl1pt bpl1ptl equ bpl1pt+2 bpl2pt equ $00e4 ; Bitplane 2 Pointer (write) bpl2pth equ bpl2pt bpl2ptl equ bpl2pt+2 bpl3pt equ $00e8 ; Bitplane 3 Pointer (write) bpl3pth equ bpl3pt bpl3ptl equ bpl3pt+2 bpl4pt equ $00ec ; Bitplane 4 Pointer (write) bpl4pth equ bpl4pt bpl4ptl equ bpl4pt+2 bpl5pt equ $00f0 ; Bitplane 5 Pointer (write) bpl5pth equ bpl5pt bpl5ptl equ bpl5pt+2 bpl6pt equ $00f4 ; Bitplane 6 Pointer (write) bpl6pth equ bpl6pt bpl6ptl equ bpl6pt+2 bplcon0 equ $0100 ; Bitplane Control Register 0 (write) bplcon1 equ $0102 ; Bitplane Control Register 1 (write) bplcon2 equ $0104 ; Bitplane Control Register 2 (write) bpl1mod equ $0108 ; Bitplane Modulo 1 (write) bpl2mod equ $010a ; Bitplane Modulo 2 (write) bpl1dat equ $0110 ; Bitplane Data Register 1 (write) bpl2dat equ $0112 ; Bitplane Data Register 2 (write) bpl3dat equ $0114 ; Bitplane Data Register 3 (write) bpl4dat equ $0116 ; Bitplane Data Register 4 (write) bpl5dat equ $0118 ; Bitplane Data Register 5 (write) bpl6dat equ $011a ; Bitplane Data Register 6 (write) spr0pt equ $0120 ; Sprite Pointer 0 (write) spr0pth equ spr0pt spr0ptl equ spr0pt+2 spr1pt equ $0124 ; Sprite Pointer 1 (write) spr1pth equ spr1pt spr1ptl equ spr1pt+2 spr2pt equ $0128 ; Sprite Pointer 2 (write) spr2pth equ spr2pt spr2ptl equ spr2pt+2 spr3pt equ $012c ; Sprite Pointer 3 (write) spr3pth equ spr3pt spr3ptl equ spr3pt+2 spr4pt equ $0130 ; Sprite Pointer 4 (write) spr4pth equ spr4pt spr4ptl equ spr4pt+2 spr5pt equ $0134 ; Sprite Pointer 5 (write) spr5pth equ spr5pt spr5ptl equ spr5pt+2 spr6pt equ $0138 ; Sprite Pointer 6 (write) spr6pth equ spr6pt spr6ptl equ spr6pt+2 spr7pt equ $013c ; Sprite Pointer 7 (write) spr7pth equ spr7pt spr7ptl equ spr7pt+2 spr0pos equ $0140 ; Sprite Position 0 (write) spr0ctl equ $0142 ; Sprite Control 0 (write) spr0data equ $0144 ; Sprite Data A Register 0 (write) spr0datb equ $0146 ; Sprite Data B Register 0 (write) spr1pos equ $0148 ; Sprite Position 1 (write) spr1ctl equ $014a ; Sprite Control 1 (write) spr1data equ $014c ; Sprite Data A Register 1 (write) spr1datb equ $014e ; Sprite Data B Register 1 (write) spr2pos equ $0150 ; Sprite Position 2 (write) spr2ctl equ $0152 ; Sprite Control 2 (write) spr2data equ $0154 ; Sprite Data A Register 2 (write) spr2datb equ $0156 ; Sprite Data B Register 2 (write) spr3pos equ $0158 ; Sprite Position 3 (write) spr3ctl equ $015a ; Sprite Control 3 (write) spr3data equ $015c ; Sprite Data A Register 3 (write) spr3datb equ $015e ; Sprite Data B Register 3 (write) spr4pos equ $0160 ; Sprite Position 4 (write) spr4ctl equ $0162 ; Sprite Control 4 (write) spr4data equ $0164 ; Sprite Data A Register 4 (write) spr4datb equ $0166 ; Sprite Data B Register 4 (write) spr5pos equ $0168 ; Sprite Position 5 (write) spr5ctl equ $016a ; Sprite Control 5 (write) spr5data equ $016c ; Sprite Data A Register 5 (write) spr5datb equ $016e ; Sprite Data B Register 5 (write) spr6pos equ $0170 ; Sprite Position 6 (write) spr6ctl equ $0172 ; Sprite Control 6 (write) spr6data equ $0174 ; Sprite Data A Register 6 (write) spr6datb equ $0176 ; Sprite Data B Register 6 (write) spr7pos equ $0178 ; Sprite Position 7 (write) spr7ctl equ $017a ; Sprite Control 7 (write) spr7data equ $017c ; Sprite Data A Register 7 (write) spr7datb equ $017e ; Sprite Data B Register 7 (write) color00 equ $0180 ; Color Register 0 (write) color01 equ $0182 ; Color Register 1 (write) color02 equ $0184 ; Color Register 2 (write) color03 equ $0186 ; Color Register 3 (write) color04 equ $0188 ; Color Register 4 (write) color05 equ $018a ; Color Register 5 (write) color06 equ $018c ; Color Register 6 (write) color07 equ $018e ; Color Register 7 (write) color08 equ $0190 ; Color Register 8 (write) color09 equ $0192 ; Color Register 9 (write) color10 equ $0194 ; Color Register 10 (write) color11 equ $0196 ; Color Register 11 (write) color12 equ $0198 ; Color Register 12 (write) color13 equ $019a ; Color Register 13 (write) color14 equ $019c ; Color Register 14 (write) color15 equ $019e ; Color Register 15 (write) color16 equ $01a0 ; Color Register 16 (write) color17 equ $01a2 ; Color Register 17 (write) color18 equ $01a4 ; Color Register 18 (write) color19 equ $01a6 ; Color Register 19 (write) color20 equ $01a8 ; Color Register 20 (write) color21 equ $01aa ; Color Register 21 (write) color22 equ $01ac ; Color Register 22 (write) color23 equ $01ae ; Color Register 23 (write) color24 equ $01b0 ; Color Register 24 (write) color25 equ $01b2 ; Color Register 25 (write) color26 equ $01b4 ; Color Register 26 (write) color27 equ $01b6 ; Color Register 27 (write) color28 equ $01b8 ; Color Register 28 (write) color29 equ $01ba ; Color Register 29 (write) color30 equ $01bc ; Color Register 30 (write) color31 equ $01be ; Color Register 31 (write) beamcon0 equ $01dc ; Video Beam Control 0 (write) *********************************************************** * CIA addresses * CIAA equ $bfe001 ; CIAA base address CIAB equ $bfd000 ; CIAB base address PRA equ $000 ; Peripheral Data Register for port A PRB equ $100 ; Peripheral Data Register for port B DDRA equ $200 ; Data Direction Register A DDRB equ $300 ; Data Direction Register B TALO equ $400 ; Timer A Low Byte TAHI equ $500 ; Timer A High Byte TBLO equ $600 ; Timer B Low Byte TBHI equ $700 ; Timer B High Byte TODLO equ $800 ; TOD Counter Low Byte TODMID equ $900 ; TOD Counter Mid Byte TODHI equ $a00 ; TOD Counter High Byte TODHR equ $b00 ; Unused SDR equ $c00 ; Serial Data Register ICR equ $d00 ; Interrupt Control Register CRA equ $e00 ; Control Register A CRB equ $f00 ; Control Register B *********************************************************** * Define the following for your coding stye: ;A5CUSTOM EQU 1 ; if a5 = $dff000 ;A5CUSTOMPLUS2 EQU 1 ; if a5 = $dff002 ;A6CUSTOM EQU 1 ; if a6 = $dff000 ;A6CUSTOMPLUS2 EQU 1 ; if a6 = $dff002 ;USEOS EQU 1 ; if you want to use graphics.library ; WaitBlit() IFND WaitVblank WaitVblank MACRO \1 .\@: IFD A5CUSTOM move.l 4(a5),d0 ELSE IFD A5CUSTOMPLUS2 move.l 4-2(a5),d0 ELSE IFD A6CUSTOM move.l 4(a6),d0 ELSE IFD A6CUSTOMPLUS2 move.l 4-2(a6),d0 ELSE move.l $dff004,d0 ENDIF ENDIF ENDIF ENDIF lsr.l #8,d0 andi.w #$3ff,d0 cmp.w \1,d0 bne.b .\@ ENDM ENDIF IFND WaitBlitter WaitBlitter MACRO IFD USEOS CALLGRAF WaitBlit ELSE IFD A5CUSTOM tst.w 2(a5) .\@: btst.b #6,2(a5) bne.b .\@ ELSE IFD A5CUSTOMPLUS2 tst.w (a5) .\@: btst.b #6,(a5) bne.b .\@ ELSE IFD A6CUSTOM tst.w 2(a6) .\@: btst.b #6,2(a6) bne.b .\@ ELSE IFD A6CUSTOMPLUS2 tst.w (a6) .\@: btst.b #6,(a6) bne.b .\@ ELSE tst.w $dff002 .\@: btst.b #6,$dff002 bne.b .\@ ENDIF ENDIF ENDIF ENDIF ENDIF ENDM ENDIF *********************************************************** ; These are the lf-codes for the blitter. With these equates you can ; do stuff like this: ; move.w #(LF_A!LF_C),bltcon0(a5) LF_A EQU $f0 LF_B EQU $cc LF_C EQU $aa