***************************************************************************** * * _| _ _ |_ |_ ' |_ _ ' * (_||_|(_|| |_ |_) | |_ / ) . | * * written by Andreas Hofbauer * copyright 1990,1991 by bsc büroautomation AG * ***************************************************************************** DUART_REGISTER MACRO UBYTE \1 UBYTE padbyte\@ ENDM STRUCTURE DUART,0 LABEL DUART_MR1 LABEL DUART_MR2 LABEL DUART_MR1A ; Mode Register A R/W DUART_REGISTER DUART_MR2A ; Synonym for above R/W LABEL DUART_SR LABEL DUART_CSR LABEL DUART_SRA ; Status Register A R DUART_REGISTER DUART_CSRA ; Clock Select Register A W LABEL DUART_CR DUART_REGISTER DUART_CRA ; Command Register A W LABEL DUART_RB LABEL DUART_TB LABEL DUART_RBA ; Receiver Buffer A R DUART_REGISTER DUART_TBA ; Transmitter Buffer A W LABEL DUART_IPCR ; Input Port Change Register R DUART_REGISTER DUART_ACR ; Auxiliary Control Register W LABEL DUART_ISR ; Interrupt Status Register R DUART_REGISTER DUART_IMR ; Interrupt Mask Register W LABEL DUART_CCR ; Current Counter Register R STRUCT DUART_CTR,4 ; Counter/Timer Register W LABEL DUART_MR1B ; Mode Register B R/W DUART_REGISTER DUART_MR2B ; Synonym for above R/W LABEL DUART_SRB ; Status Register B R DUART_REGISTER DUART_CSRB ; Clock Select Register B W DUART_REGISTER DUART_CRB ; Command Register B W LABEL DUART_RBB ; Receiver Buffer B R DUART_REGISTER DUART_TBB ; Transmitter Buffer B W DUART_REGISTER DUART_IVR ; Interrupt Vector Register R/W LABEL DUART_IPR ; Input Port Register (Unlatched) R DUART_REGISTER DUART_OPCR ; Output Port Configuration Register W LABEL DUART_Start ; Start Counter Command R DUART_REGISTER DUART_SetOPR ; Set Bit Output Port Register W LABEL DUART_Stop ; Stop Counter Command R DUART_REGISTER DUART_ClrOPR ; Clear Bit Output Port Register W LABEL DUART_SIZEOF ; Bits of Mode Register 1 A (MR1A) and Mode Register 1 B (MR1B) MR1F_Bits EQU %00000011 MR1F_5Bits EQU %00000000 MR1F_6Bits EQU %00000001 MR1F_7Bits EQU %00000010 MR1F_8Bits EQU %00000011 BITDEF MR1,PartyOdd,2 MR1F_Party EQU %00011000 MR1F_WithParty EQU %00000000 MR1F_ForceParty EQU %00001000 MR1F_NoParty EQU %00010000 MR1F_Multidrop EQU %00011000 BITDEF MR1,BlockErr,5 BITDEF MR1,FFULLIRQ,6 BITDEF MR1,EnableRxRTS,7 ; Bits of Mode Register 2 A (MR2A) and Mode Register 2 B (MR2B) MR2F_Stops EQU %00001111 MR2F_1Stop EQU %00000111 MR2F_2Stops EQU %00001111 BITDEF MR2,EnableCTS,4 BITDEF MR2,EnableTxRTS,5 MR2F_Mode EQU %11000000 MR2F_Normal EQU %00000000 MR2F_Echo EQU %01000000 MR2F_LocalLoop EQU %10000000 MR2F_RemoteLoop EQU %11000000 ; Bits of the Status Register A and B BITDEF SR,RxRDY,0 BITDEF SR,FFULL,1 BITDEF SR,TxRDY,2 BITDEF SR,TxEMT,3 BITDEF SR,Overrun,4 BITDEF SR,Party,5 BITDEF SR,Framing,6 BITDEF SR,Break,7 ; Fields for the Command Register A and B CRF_RxCommand EQU %00000011 CRF_RxNone EQU %00000000 CRF_RxEnable EQU %00000001 CRF_RxDisable EQU %00000010 CRF_TxCommand EQU %00001100 CRF_TxNone EQU %00000000 CRF_TxEnable EQU %00000100 CRF_TxDisable EQU %00001000 CRF_MiscCommand EQU %01110000 CRF_MiscNone EQU %00000000 CRF_MiscResetMR EQU %00010000 CRF_MiscResetRx EQU %00100000 CRF_MiscResetTx EQU %00110000 CRF_MiscResetErr EQU %01000000 CRF_MiscResetBrk EQU %01010000 CRF_MiscStartBrk EQU %01100000 CRF_MiscStopBrk EQU %01110000