#ifndef SUPERGEN_SUPERGEN_H #define SUPERGEN_SUPERGEN_H /************************************************************************ ** ** ** supergen.h -- supergen.library declarations ** ** ** ** v3.0 ** ** ** ** 13 Dec 1991 - Bill Barton - slight revisions (v3.0) ** ** 15 Aug 1989 - Bill Barton - revised for SuperGen 2000s (v2.0) ** ** 30 Dec 1987 - John Botteri - created this file ** ** ** ** Copyright (C) 1987-1991 Digital Creations, Inc. ** ** All rights reserved. ** ** ** ************************************************************************/ #ifndef EXEC_TYPES_H #include #endif /************************************************************************ ** ** ** Misc. Definitions ** ** ** ************************************************************************/ #define SUPERGEN_Minimum 2 /* Minimum supported library version */ /************************************************************************ ** ** ** Misc. SuperGen() Definitions ** ** ** ************************************************************************/ /* Mode values */ #define SGM_Software 1 #define SGM_Manual 0 /* Fader values are in terms of how much external video is shown: value pos amiga video ----- --- ----- ----- SGF_Min up max min SGF_Max down min max */ #define SGF_Min 0 /* Min fader value */ #define SGF_Max 63 /* Max fader value */ #define SGF_Up SGF_Min #define SGF_Down SGF_Max #define SGF_Amiga SGF_Min /* Fader value for full Amiga graphics */ #define SGF_Video SGF_Max /* Fader value for full external video */ /* Time values */ #define SGT_NoChange -1 /* Value for SuperGen() Time arguments to prevent corresponding fader from being affected */ /************************************************************************ ** ** ** SuperGen 2000s Register Definitions ** ** ** ** Examples: ** ** ** ** Set the V-Phase portion of Sat & V-Phase register: ** ** ** ** SGSetRegister (vphase << SGSVP_VPhase_Shift, ** ** SGSVP_VPhase_Mask, SGR_SatVPhase); ** ** ** ** Read the V-Phase portion of Sat & V-Phase register: ** ** ** ** result = SGSetRegister (0, 0, SGR_SatVPhase); ** ** vphase = (result & SGSVP_VPhase_Mask) ** ** >> SGSVP_VPhase_Shift; ** ** ** ************************************************************************/ /* Register Numbers */ #define SGR_Dissolve 0 /* Dissolve fader values (6/6) */ #define SGR_Control 1 /* Control Register (12) */ #define SGR_CPhase 2 /* Chroma Phase Fine/Coarse (8/3) */ #define SGR_SatVPhase 3 /* Saturation and V-Phase (8/4) */ #define SGR_HPhase 4 /* Horizontal Phase Adjust (12) */ #define SGR_Null -1 /* special register number */ /* Register mask bits */ #define SGRF_Dissolve (1 << SGR_Dissolve) #define SGRF_Control (1 << SGR_Control) #define SGRF_CPhase (1 << SGR_CPhase) #define SGRF_SatVPhase (1 << SGR_SatVPhase) #define SGRF_HPhase (1 << SGR_HPhase) /* Dissolve Register (SGR_Dissolve) 11 10 9 8 7 6 5 4 3 2 1 0 +-----------------+-----------------+ | Background | Foreground | +-----------------+-----------------+ This register also exists on the SG-10 and is normally controlled by the SuperGen() function. NOTE: Writing to this register with SGSetRegister() affects the behavior of SuperGen(): . Setting this register while in SGM_Manual mode will set the mode to SGM_Software. . Setting this register during a dissolve effect will load the new value into the dissolve register and terminate the dissolve effect (sending signals where appropriate). Calling SGSetRegister() with SGR_Null for the register number will revert to SGM_Manual mode. Reading this register is harmless. In most cases this register will contain the last value set by the dissolve ramp generator. However if the SuperGen() mode is set to SGM_Manual during a dissolve effect, the values returned by StatusGen() may not match the contents of this register. */ #define SGDIS_FG_Shift 0 #define SGDIS_FG_Bits 6 #define SGDIS_FG_Mask 0x03f #define SGDIS_BG_Shift 6 #define SGDIS_BG_Bits 6 #define SGDIS_BG_Mask 0xfc0 /* Control Register (SGR_Control) 11 10 9 8 7 6 5 4 3 2 1 0 +-----------------------------------+ | Control Bits | +-----------------------------------+ NOTES ----- 1. The Dissolve Hold bit is automatically managed by calls to SuperGen...() to keep it in sync with the software dissolve mode. 2. Some bits are interrelated. AlphaKey and AutoDissolve: AK AD Mode -- -- ---- 0 0 Amiga key, normal dissolve 0 1 Amiga key, interpretive dissolve 1 0 External Alpha key 1 1 Future Expansion (DON'T USE) BlankSelect and VIPass: BS VI Mode -- -- ---- 0 x External blanking 1 0 Internal blanking, pass v-lines 10-21 1 1 Internal blanking See the SuperGen 2000s manual for more detail about how these controls behave. */ #define SGCR_Mask 0xfff /* use this mask when reading the current control bit settings */ /* bit numbers */ /* Bit Discription 0 1 */ /* --------------------- ------- ------- */ #define SGCRB_AGC 0 /* Auto Gain Chroma Off On */ #define SGCRB_IntKey 1 /* Internal Key Enable Disable */ #define SGCRB_DissolveHold 2 /* Dissolve Hold Mode Off On */ #define SGCRB_VIPass 3 /* Vert. Interval Pass On Off */ #define SGCRB_BlankSelect 4 /* Blank Select Ext. Int. */ #define SGCRB_AlphaKey 5 /* Alpha Key Disable Enable */ #define SGCRB_RGBTerm 6 /* RGB Termination Enable Disable */ #define SGCRB_FastClamp 7 /* Fast Sync Tip Clamp Disable Enable */ #define SGCRB_NotchFilter 8 /* Notch Filter Disable Enable */ #define SGCRB_TimingMode 9 /* Timing Mode Disable Enable */ #define SGCRB_AutoDissolve 10 /* Auto (interpretive) Dissolve Disable Enable */ #define SGCRB_SetupAdder 11 /* Setup (7.5 IRE) Adder Enable Disable */ /* masks */ #define SGCRF_AGC (1 << SGCRB_AGC) #define SGCRF_IntKey (1 << SGCRB_IntKey) #define SGCRF_DissolveHold (1 << SGCRB_DissolveHold) #define SGCRF_VIPass (1 << SGCRB_VIPass) #define SGCRF_BlankSelect (1 << SGCRB_BlankSelect) #define SGCRF_AlphaKey (1 << SGCRB_AlphaKey) #define SGCRF_RGBTerm (1 << SGCRB_RGBTerm) #define SGCRF_FastClamp (1 << SGCRB_FastClamp) #define SGCRF_NotchFilter (1 << SGCRB_NotchFilter) #define SGCRF_TimingMode (1 << SGCRB_TimingMode) #define SGCRF_AutoDissolve (1 << SGCRB_AutoDissolve) #define SGCRF_SetupAdder (1 << SGCRB_SetupAdder) /* control values (based on bit descriptions above) */ /* note that some of the bits are negative logic! */ #define SGCR_AGC_On SGCRF_AGC #define SGCR_AGC_Off 0 #define SGCR_IntKey_On 0 #define SGCR_IntKey_Off SGCRF_IntKey #define SGCR_DissolveHold_On SGCRF_DissolveHold #define SGCR_DissolveHold_Off 0 #define SGCR_VIPass_On 0 #define SGCR_VIPass_Off SGCRF_VIPass #define SGCR_IntBlank SGCRF_BlankSelect #define SGCR_ExtBlank 0 #define SGCR_AlphaKey_On SGCRF_AlphaKey #define SGCR_AlphaKey_Off 0 #define SGCR_RGBTerm_On 0 #define SGCR_RGBTerm_Off SGCRF_RGBTerm #define SGCR_FastClamp_On SGCRF_FastClamp #define SGCR_FastClamp_Off 0 #define SGCR_NotchFilter_On SGCRF_NotchFilter #define SGCR_NotchFilter_Off 0 #define SGCR_TimingMode_On SGCRF_TimingMode #define SGCR_TimingMode_Off 0 #define SGCR_AutoDissolve_On SGCRF_AutoDissolve #define SGCR_AutoDissolve_Off 0 #define SGCR_SetupAdder_On 0 #define SGCR_SetupAdder_Off SGCRF_SetupAdder /* Saturation and V-Phase Register (SGR_SatVPhase) 11 10 9 8 7 6 5 4 3 2 1 0 +-----------+-----------------------+ | V-Phase | Saturation | +-----------+-----------------------+ */ #define SGSVP_Sat_Shift 0 #define SGSVP_Sat_Bits 8 #define SGSVP_Sat_Mask 0x0ff #define SGSVP_VPhase_Shift 8 #define SGSVP_VPhase_Bits 4 #define SGSVP_VPhase_Mask 0xf00 /* Chroma Phase Register (SGR_CPhase) 11 10 9 8 7 6 5 4 3 2 1 0 +--+--------+-----------------------+ |SP| Coarse | Fine Tune | +--+--------+-----------------------+ SP is an unused (Spare) Bit. Don't set it. */ #define SGCPH_Fine_Shift 0 #define SGCPH_Fine_Bits 8 #define SGCPH_Fine_Mask 0x0ff #define SGCPH_Coarse_Shift 8 #define SGCPH_Coarse_Bits 3 #define SGCPH_Coarse_Mask 0x700 /* Horizontal Phase Adjust (SGR_HPhase) 11 10 9 8 7 6 5 4 3 2 1 0 +-----------------------------------+ | Horizontal Phase | +-----------------------------------+ */ #define SGHPH_Shift 0 #define SGHPH_Bits 12 #define SGHPH_Mask 0xfff /************************************************************************ ** ** ** SuperGenInfo ** ** ** ** Structure returned by SuperGenType(). ** ** ** ** All fields must be considered READ ONLY and some fields ** ** contain private data. The only fields that you should read ** ** are Model, Flags, RegMask, and Name. ** ** ** ************************************************************************/ struct GenRegister { /* hardware register data */ UWORD gr_Reg; UWORD gr_Mask; }; struct SuperGenInfo { ULONG Ident; /* SGEN */ struct GenRegister Regs[8]; /* hardware register shadows (PRIVATE!) */ UWORD Model; /* Model number (one of the SGMODEL_ #'s) */ UBYTE Flags; /* currently 0, for future expansion */ UBYTE RegMask; /* which registers are supported (SGRF_ bits) */ char Name[32]; }; #define SGEN ( (ULONG)'S'<<24 | (ULONG)'G'<<16 | 'E'<<8 | 'N' ) /* SGEN magic # */ #define SGMODEL_SuperGen 10 /* original SuperGen */ #define SGMODEL_2000s 2000 /* SuperGen 2000s */ /************************************************************************ ** ** ** Macros ** ** ** ** See supergen.doc for complete documenation. ** ** ** ************************************************************************/ #define SGManual() SuperGen (SGM_Manual, 0, SGT_NoChange, 0, SGT_NoChange) #define SGSTAT_FG(stat) ((UBYTE)(stat)) #define SGSTAT_BG(stat) ((UBYTE)((stat) >> 8)) #define SGSTAT_Enable(stat) ((UBYTE)((stat) >> 16)) #define SGGetRegister(reg) SGSetRegister (0, 0, (reg)) #endif