Genlock circuit operation description ----------------------------------------------------------- Enhancements: One feature that space does not allow for now is the ability to have software control of pixel switch disable. Now this is done with a mechanical switch. Pixel switch disable allows the user to completely ignore background video, yet have the Amiga computer genlocked. This eliminates the problem of software having to be written with genlock in mind. It would add $5-$10 to cost of goods. The control bits would be encoded in the vertical interval, as audio on/off is presently done. Eight to sixteen functions (bits) could be controlled once this ability is on the board. CHROMA KEY -- since all signals are in RGB format, it would be easy to selectively insert video based on color level. Additional circuitry would add about $10, but would not fit in the existing case. ============================================================ Circuit description The purpose of the genlock peripheral is to synchronize the video output of the Amiga computer with another video source such as camera, broadcast, or VCR. Circuitry inside the peripheral allows for the overlay of computer graphics on whatever video source is connected. Also provided are facilities for stereo mixing of computer and source audio. Input to the genlock peripheral is composite source and analog RGB computer video. Output video is in the forms of composite and analog RGB for high-resolution viewing on an RGB monitor. Also output are a master 28.636363 MHZ computer clock, H/2, and V/2 video resets required to synchronize the computer's graphic devices. Power for this device is derived from computer +5, +12, -5 volts D.C. rails. Circuitry in the peripheral is divided into several main functions which are: 1) regenerating the horizontal and vertical components of the original composite source video, (2) phase locking the 28 MHZ clock to input video horizontal timing, (3) combining source and computer video, (4) mixing source and computer audio, (5) and encoding the RGB overlayed video into NTSC or PAL. (1) REGENERATING HORIZONTAL AND VERTICAL TIMING Source composite video enter on J1. Transistors Q16 and Q7 form a feedback amplifier with a gain of 3. Simple sync tip clamping is provided by CR3, whose clamp voltage is set by CR4. The net effect is to clamp sync tips at around 0 volts. Comparator U3 strips the sync off of the clamped composite video on it's pin 4. Comparator trip point is set by resistive divider R55 and R49 to be at about the 50% amplitude point on the sync. On the output of U3 (pin 9) is composite sync at TTL levels. One-shot U1 is a digital integrator designed to detect when video drops out for more than 12 lines. The output of this detector forces crystal mode operation (Q4 enables power to the crystal oscillator) and selects computer composite sync (J8-19) to insure a stable monitor picture. Nand gates in U5 form the sync selector logic. The composite sync output of selector U5 is decoded into its horizontal and vertical components. The time constants of differentiator C21/R56 and one-shot U12 are chosen to trigger only on the horizontal components of sync. Output on U12 pin 5 is a series of pulses at a horizontal rate. One-shot U19 forms a negative going pulse 4.7 microseconds wide buffered by U23 for monitors requiring seperate horizontal sync (J10-11). The time constants of integrator R77/R76 /C34 and one-shot U12 are chosen to trigger only on the vertical component of composite sync. The output on U12 pin 4 is a pulse 90 microseconds wide on line 3 every vertical interval. One-shot U19 generates a negative pulse 200 microseconds wide buffered U23 for monitors requiring seperate vertical sync (J10-10). The graphic devices in the Amiga computer require reset every other vertical interval in genlock mode. Dual-D flip flop U15 performs this task. It is basically wired as a divide by 2 with horizontal sync clocking the first stage. This causes the V/2 reset pulse to be synchronous with horizontal, one line wide, retiming its edges. V/2 reset is buffered by R10 because at times the Amiga computer will output vertical pulses on J9-23, (ie. genlock mode not selected with peripheral attached). The sandcastle generator is made up of U2, U7, Q5, and Q6. This circuitry generates a multi-level pulse, encoding burst and blanking timing information for U8, the chroma decoder. One-shot U2 time constants are chosen to generate the blanking portion of the sandcastle pulse. One-shot U7 time constants are chosen to generate burst timing. Transistor pair Q5 and Q6 form a low impedance wide-band inverting summing amplifier. R27 supplies a D.C. offset to give the correct D.C. levels at Q6 collector for U8. R26 and R31 sum in the blanking and burst signals respectively. The gain of any signal to this amplifier is set by the ratio of the input series resistor (R26, R31, R27) to feedback resistor R28. The sandcastle pulse at Q6 collector encodes blanking information from 0-5V dc and burst timing from 5-10V dc, with the pulse looking very much like it's name implies. H/2 reset is generated by U14 and U17. The input to one-shot U14 is regenerated horizontal from the 28 MHZ phase-locked loop. U14 time constant is 33 microseconds, making a square wave at horizontal rate on pin 12. Dual D-type flip flop U17 is wired as a gated divide by 2. The H/2 reset output (J9-21) is a negative going pulse 32 microseconds wide, with the edges retimed to the Amiga computer color clock (J9-6). This re-timing to color clock is required to guard against metaphysical states in the Amiga graphical devices. (2) 28 MHZ PHASE LOCKED LOOP The circuitry to generate the 28.636363 MHZ clock is comprised of the voltage controlled/crystal oscillators, phase detector, and divider, the classic phase-locked loop. The VCO has some unique features. The genlock peripheral must generate a stable master clock, allowed to vary only a few percent in genlock mode. When there is no video on the peripheral input, crystal stability is required for real-time clocks and counters. To complicate things the Amiga computer cannot tolerate large timing variations when switching in and out of genlock mode, missing a clock cycle is catastrophic. Therefore, a circuit was designed so that a crystal oscillator can "tickle" the voltage controlled oscillator for completely synchronous mode switching. Q24 and its associated circuitry is the 28 MHZ Colpitts crystal oscillator. Q23 is a buffer to prevent loading of Q24. Power for Q23 and Q24 is controlled by Q4, supplying current only when there is no input video (xtal mode required). Q13 and its associated components form a Colpitts voltage controlled oscillator. The frequency is changed by varying the D.C. control voltage on CR7, a varactor diode. C60 varies the VCO center frequency. The connection made by C63 and R128 allows the crystal oscillator to "tickle" the VCO. For an in-depth discussion on oscillators, consult "Crystal oscillator Circuits" by Robert J. Matthys. Q12 buffers the 28 MHZ clock to the Amiga, (J9-1) setting the correct TTL levels with R64 and R65. L2 and C41 filter the 28 MHZ to reduce RFI. A synchronous divide by 1820 is formed by U6, U10, U13, U16, U4. U16 is a schottky device because of the frequency involved. Operation of this circuit is straightforward. The output of U6 pin 13 is a stream of pulses at a horizontal rate. This is called regenerated horizontal and is never interrupted, an Amiga requirement. This signal is one input to the phase detector. The phase detector used is the analog sample and hold type. Basically, this detector works by sampling a ramp generated from one comparison frequency (feedback) with a sample pulse derived from the other (reference). The output D.C. is used to control the VCO. The reference input for this phase detector is the horizontal component of input video, applied to one-shot U11 pin 1. Delay in U11 is about 1/2 line, with a potentiometer to fine tune horizontal position, R133. U14 generates a short sample pulse (275 nanoseconds), level shifted by Q14. Q14 collector drives sample gate Q25, with the sample voltage held on C78. The feedback input goes to the other section of U11, again adding a 1/2 line delay. The output of U11 is used to trigger the ramp generator formed by Q21 and Q22. Ramp charge time is controlled by C52 and is designed to accomodate the large timebase errors present in VCR playback. Ramp charge time is critical in PLL design: steeper ramp means high gain and less lock range, slower ramp means lower gain but increase in tracking range. The D.C. operating point for this loop is determined by a voltage divider formed by R106, R156, and R157. It is chosen to give maximum dynamic range. Error signal on C78 is buffered by dual op-amp U20, section 1. Loop time constants are determined by the R105, C61, C67, R131 around section 2 of U20. The output of this section drives the VCO, closing the control loop. (3) COMBINING SOURCE AND COMPUTER VIDEO Now that the Amiga computer is synchronous with the source video, computer and source video is combined. U8 alone performs the overlay function. The main function of U8 (TDA3301) is to decode composite video into its red, green, and blue components. First, source video is split apart into chrominance and luminance. Network L1, C27 and R52 filters out chroma, passing luminence only information to U8-37. Network R83, L3, C43, and C28 passes only chroma information to U8-1. U8 also internally has a 3.579545 MHZ PLL. By utilizing luminance, chrominance, sandcastle pulse, frame pulse (U28-29) and an internal PLL, video is decoded. U8 also has inputs for external analog RGB video. Computer RGB is applied to U8 pins 25, 26, and 24 respectively. The signal that determines if source on computer video is ultimately output is pixel switch (J9-4). This is a software generated control line from the Amiga. One section of gate U5 is used to force pixel switch to show only computer video when source video is lost. Each video output of U8 is D.C. clamped for black level stability. The following is a description of just the blue channel. Blue video exits U8 on pin 14. The level is divided down by resistors R71 and R72 and feedback to pin 16 completing the loop. C25 is used to hold the sampled clamp value (see Motorola data sheet for full details). The blue video is then amplified X2 by transistor feedback pair Q10 and Q11. Gain is set by the ratio of R60/R61. R63 gives the characteristic line impedance of 75 ohms (J10-5). Operation is similar for the green and red channels. Other components around U8 are best understood by consulting the TDA3301 data sheet. A hue control (R134) is provided to allow user color matching of computer and source video. (4) MIXING SOURCE AND COMPUTER AUDIO The left audio channel mixer is described. Source audio (J3) is capacitivly coupled by C82 and terminated in an impedance of 47K. Electronic switch U22 (CD4066BE) is used to disable source audio via computer control. It operates as follows. The control to enable/disable source audio is encoded in the vertical and horizontal blanking interval of the pixel switch line, software setable on the Amiga computer. U18 samples pixel switch during the vertical interval, using the frame pulse to latch audio status. The latched output (U18 pins 6&5) is used to control transmission gates in U22. Data is latched on or about line number 10. No horizontal sampling is done. Computer audio enter on J5. Passive mixing network R140, 141, 143, 142 and control R132 combines the two sources. Pot R132 allows user control relative levels. Right and left mixing is controlled by the same shaft. Feedback pair Q19 and Q20 provide gain (x3) to make up for losses in the passive mixer. C83 provides bandlimiting (20KHZ) to reduce noise pick-up within the box. Audio and video grounds are kept seperate until the connector (J9). (5) ENCODING THE RGB VIDEO Analog RGB signals are encoded into NTSC or PAL by a single device (U21) from Motorola, number MC1377. This IC requires only continuous subcarrier and composite sync to output composite video. Subcarrier is obtained from the oscillator in U8, coupled by C45. Sync comes from the output of selector U5. The analog RGB signals (0-1v amp.) from U8 are coupled into pins 3,5 and 4 of U21. Inside the MC1377 a resistive matrix and multipliers transform RGB into an encoded chroma signal, output on pin 13. To reduce interference with high frequency luminance information, the chroma is bandpass filtered to 1 MHZ by T1, R11, C72, and C70. Chroma re-enters the chip on pin 10. The luminance signal is derived via an internal matrix from the RGB input?? output inverted on pin 6. TD1 delays the luminance information by 400 ns making up the time delay caused in the chroma path by the bandpass filter. Chroma and luma are summed and clamped inside U21, emerging on pin 9 as composite video. Emitter follower Q15 buffers the video to J6. Color burst is also added to the video inside U21. External components R95 and C69 determine burst position. Pin 16 is a stable zener derived 8.5 volts. If you would like to receive your own hard-copy of this spec, please leave email in mailbox 'techs' IMPORTANT: Please make our job easier by including the word 'genlock' somewhere in the Subject line!! Don't forget to leave your name and address. I didn't leave out much, the table of contents, a short discussion of possible uses, a diagram that shows the location of each connector (to be posted next week) and a drawing the shows the genlock box and its mechanical interface. Thank you, Randy Weiner <> Commodore Technical Support The following material is excerpted from the preliminary Genlock spec. Please excuse any non-obvious typos, it will take me a week to uncross my eyes. Thank you , Randy Weiner 'rweiner' Excerpts from the Amiga Genlock Peripheral Specification CONNECTORS ================================================== Female 23-pin "D" type (to computer) -------------------------------------------------- pin 1 : 28.636360 MHZ clock out 2 : external clock enable out 3 : red analog video in 4 : green analog video in 5 : blue analog video in 6,7,8,9 : no connection 10: composite sync in 11: H/2 reset out 12: V/2 reset out 13: ground 14: pixel switch in 15: color clock (3.58 MHZ) in 16,17: ground 18,19: ground 20: ground 21: -5 volts in 22: +12 volts in 23: +5 volts in Male 23-pin "D" type (to monitor) -------------------------------------------------- pin 1 : no connection 2 : no connection 3 : red analog video out 4 : green analog video out 5 : blue analog video out 6,7,8,9 : no connection 10: composite sync out 11: horizontal sync out 12: vertical sync out 13: ground 14,15: no connection 16,17: ground 18,19: ground 20: ground 21,22,23: no connection RCA-type jacks (8) -------------------------------------------------- 1 : composite source video in 2 : composite video out 3 : R-source audio in 4 : L-source audio in 5 : R-computer audio in 6 : L-computer audio in 7 : R-mixed audio out 8 : L-mixed audio out VIDEO PERFORMANCE ================================================== Bandwith: composite -3db luminance at 8 MHZ Analog RGB -3db at 8 MHZ Chroma I&Q -3db at 0.5 MHZ Locking Range: Horizontal +/- 2% from 15735 HZ Subcarrier +/- 300 HZ from 3.579545 MHZ Vertical crash lock Horizontal phase +/- 1.5 microseconds Subcarrier phase +/- 45 degrees from burst Timing: Vertical reset output is 3 lines late Horizontal reset output is coincident with input Clock jitter <10ns, 5ns typ. in genlock, crystal stable with no video source 28 MHZ clock in genlock mode, is phase locked to input horizontal timing. Automatic switch over to crystal mode occurs in 10 lines of missing source video. No discontinuity in clock cycles occurs. AUDIO PERFORMANCE ================================================== Bandwidth: -3db at 12 HZ and 500 KHZ, flat with 2db Gain: 0 to -50db dependent on mix control setting source audio can be disabled (-50db) by setting a bit in pixel switch line during vertical blanking INPUT SPECIFICATIONS ================================================== Female 23-pin "D" type (to computer) -------------------------------------------------- pin 3 : analog red -- terminated in 75 ohms, inut level of 1 volt p-p nominal level. 4 : analog green -- same as analog red 5 : analog blue -- same as analog red 10: composite sync -- TTL level, 10K load, negative going 14: pixel switch -- TTL level, 1K load, low level enables external RGB for overlay. During vertical interval, a low level of pixel switch enables external audio, high level disables. This level is valid during horizontal and vertical blanking. 15: color clock -- TTL level, 4K load, should be synchronous with host computer, freq. of 3.579545 MHZ. 21: -5 volts, approx. 50ma load. 22: +12 volts, approx. 250ma load. 23: +5 volts, approx. 300ma load. RCA type jacks -------------------------------------------------- composite video -- 75 ohm load, 1 volt p-p, 0.3 volt sync, +/- 6db, will accept block vertical R-source audio -- 4000 ohm load, 1 volt rms nominal L-source audio -- same as above R-computer audio -- same as above L-computer audio -- same as above OUTPUT SPECIFICATIONS ================================================== Female 23-pin "D" type (to computer) -------------------------------------------------- pin 1 : 28.636360 clock -- semi-sinusoid, able to drive two schottky TTL loads 2 : external clock enable -- low active, direct connect. to gnd. 11: horizontal reset out -- low active, 'LS244 driver, low for 32 microseconds at beginning of a horizontal line. 12: vertical reset out -- low active, 'LS244 driver, occurs on line 3, 30 microseconds wide. Male 23-pin "D" type (to monitor) -------------------------------------------------- pin 3 : red analog video - 75 ohm impedance, will drive 1 volt p-p into 75 ohms load 4 : green analog video - same as pin 3 5 : blue analog video - same as pin 3 10: composite sync -- low active, 'LS244 driver 11: horizontal sync -- low active, 'LS244 driver, 4.7 microseconds wide 12: vertical sync -- low active, 'LS244 driver, 3 horizontal lines wide. RCA jacks -------------------------------------------------- composite video out - 75 ohm impedance, 1 volt p-p into 75 ohm load, 0.3 volts sync. R-mixed audio -- 100 ohm impedance, 1 volt RMS into 600 ohms. L-mixed audio -- same as above