**********************************************************************
*                                                                    *
* This is a collection of code segments to cause CPU exceptions      *
* This is just a representative selection of of possible exceptions  *
*                                                                    *
**********************************************************************

		XDEF	_address_exc,_illegal_exc,_div0_exc,_chk_exc
		XDEF	_trapv_exc,_privelege_exc,_trace_exc
		XDEF	_A_Line_exc,_F_Line_exc,_trap1_exc

* ------------------------------------------------------------------ *

* Create address CPU exception #3

* On a 68000 access of data at an odd address will create exception #3
* On later processors this is legal though slower
* On all processors it is illegal for an instruction to be at an odd address

_address_exc	dc.w	$6003	;bra.b	*+5 0x6003 =branch to an odd address

* ------------------------------------------------------------------ *

* Create illegal CPU exception #4

_illegal_exc	ILLEGAL			;0x4afc Motorola "illegal" instruction


* ------------------------------------------------------------------ *

* Create a division by zero CPU exception #5

_div0_exc	moveq.l	#0,d0		;0x7000
		divu	d0,d1		;0x82c0		=divide d1 by zero

* ------------------------------------------------------------------ *

* Create a CHK CPU exception #6

_chk_exc	moveq.l	#$ff,d0		;0x70ff	;d0 value less than zero
		chk	(a0),d0		;4190	;so chk gives an exception



* ------------------------------------------------------------------ *

* Create a trapv CPU exception #7

_trapv_exc	ori.w #%00000010,CCR	;0x003c, 0x0002	=Set V status flag
		trapv			;0x4e76


* ------------------------------------------------------------------ *

* Create a privelege CPU exception #8

* move to SR can only be executed in supervisor mode (ALL CPU's)

_privelege_exc	moveq.l	#0,d0		;0x7000

* If supervisor mode, change to user mode
* If already user mode, exception generated here
		move	d0,SR		;0x46c0

* Now definitely user mode so exception generated if it gets here!
		move	d0,SR		;0x46c0


* ------------------------------------------------------------------ *


* Create a trace CPU exception #9

_trace_exc	move.l  (4).w,a6	;0x2c78, 0x0004
		move.l  #$8000,d0	;0x203c, 0x0000, 0x8000	=Trace bit
		move.l  #$ffff,d1	;0x223c, 0x0000, 0xffff
		jsr     $ffffff70(a6)	;0x4eae, 0xff70	=SetSR(newSR,mask)
		rts			;0x4e75			d0    d1



* ------------------------------------------------------------------ *

* Create a Line-A exception #10

* This only creates this exception with a standard 68000 machine

_A_Line_exc	dc.l	$a2222222	;0xa2222222



* ------------------------------------------------------------------ *

* Create a Line-F exception #11


_F_Line_exc	dc.l	$f2222222	;0xf2222222


* ------------------------------------------------------------------ *

* Create a trap #1 exception #33

_trap1_exc		trap	#1	;0x4e41